1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_plat.h>
26 #include <asm/smp_scu.h>
27 #include <asm/firmware.h>
34 extern void exynos4_secondary_startup(void);
36 static inline void __iomem
*cpu_boot_reg_base(void)
38 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1
)
43 static inline void __iomem
*cpu_boot_reg(int cpu
)
45 void __iomem
*boot_reg
;
47 boot_reg
= cpu_boot_reg_base();
48 if (soc_is_exynos4412())
50 else if (soc_is_exynos5420())
56 * Write pen_release in a way that is guaranteed to be visible to all
57 * observers, irrespective of whether they're taking part in coherency
58 * or not. This is necessary for the hotplug code to work reliably.
60 static void write_pen_release(int val
)
64 sync_cache_w(&pen_release
);
67 static void __iomem
*scu_base_addr(void)
69 return (void __iomem
*)(S5P_VA_SCU
);
72 static DEFINE_SPINLOCK(boot_lock
);
74 static void exynos_secondary_init(unsigned int cpu
)
77 * let the primary processor know we're out of the
78 * pen, then head off into the C entry point
80 write_pen_release(-1);
83 * Synchronise with the boot thread.
85 spin_lock(&boot_lock
);
86 spin_unlock(&boot_lock
);
89 static int exynos_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
91 unsigned long timeout
;
92 unsigned long phys_cpu
= cpu_logical_map(cpu
);
95 * Set synchronisation state between this boot processor
96 * and the secondary one
98 spin_lock(&boot_lock
);
101 * The secondary processor is waiting to be released from
102 * the holding pen - release it, then wait for it to flag
103 * that it has been released by resetting pen_release.
105 * Note that "pen_release" is the hardware CPU ID, whereas
106 * "cpu" is Linux's internal ID.
108 write_pen_release(phys_cpu
);
110 if (!(__raw_readl(S5P_ARM_CORE1_STATUS
) & S5P_CORE_LOCAL_PWR_EN
)) {
111 __raw_writel(S5P_CORE_LOCAL_PWR_EN
,
112 S5P_ARM_CORE1_CONFIGURATION
);
116 /* wait max 10 ms until cpu1 is on */
117 while ((__raw_readl(S5P_ARM_CORE1_STATUS
)
118 & S5P_CORE_LOCAL_PWR_EN
) != S5P_CORE_LOCAL_PWR_EN
) {
126 printk(KERN_ERR
"cpu1 power enable failed");
127 spin_unlock(&boot_lock
);
132 * Send the secondary CPU a soft interrupt, thereby causing
133 * the boot monitor to read the system wide flags register,
134 * and branch to the address found there.
137 timeout
= jiffies
+ (1 * HZ
);
138 while (time_before(jiffies
, timeout
)) {
139 unsigned long boot_addr
;
143 boot_addr
= virt_to_phys(exynos4_secondary_startup
);
146 * Try to set boot address using firmware first
147 * and fall back to boot register if it fails.
149 if (call_firmware_op(set_cpu_boot_addr
, phys_cpu
, boot_addr
))
150 __raw_writel(boot_addr
, cpu_boot_reg(phys_cpu
));
152 call_firmware_op(cpu_boot
, phys_cpu
);
154 arch_send_wakeup_ipi_mask(cpumask_of(cpu
));
156 if (pen_release
== -1)
163 * now the secondary core is starting up let it run its
164 * calibrations, then wait for it to finish
166 spin_unlock(&boot_lock
);
168 return pen_release
!= -1 ? -ENOSYS
: 0;
172 * Initialise the CPU possible map early - this describes the CPUs
173 * which may be present or become present in the system.
176 static void __init
exynos_smp_init_cpus(void)
178 void __iomem
*scu_base
= scu_base_addr();
179 unsigned int i
, ncores
;
181 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9
)
182 ncores
= scu_base
? scu_get_core_count(scu_base
) : 1;
185 * CPU Nodes are passed thru DT and set_cpu_possible
186 * is set by "arm_dt_init_cpu_maps".
191 if (ncores
> nr_cpu_ids
) {
192 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
197 for (i
= 0; i
< ncores
; i
++)
198 set_cpu_possible(i
, true);
201 static void __init
exynos_smp_prepare_cpus(unsigned int max_cpus
)
205 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9
)
206 scu_enable(scu_base_addr());
209 * Write the address of secondary startup into the
210 * system-wide flags register. The boot monitor waits
211 * until it receives a soft interrupt, and then the
212 * secondary CPU branches to this address.
214 * Try using firmware operation first and fall back to
215 * boot register if it fails.
217 for (i
= 1; i
< max_cpus
; ++i
) {
218 unsigned long phys_cpu
;
219 unsigned long boot_addr
;
221 phys_cpu
= cpu_logical_map(i
);
222 boot_addr
= virt_to_phys(exynos4_secondary_startup
);
224 if (call_firmware_op(set_cpu_boot_addr
, phys_cpu
, boot_addr
))
225 __raw_writel(boot_addr
, cpu_boot_reg(phys_cpu
));
229 struct smp_operations exynos_smp_ops __initdata
= {
230 .smp_init_cpus
= exynos_smp_init_cpus
,
231 .smp_prepare_cpus
= exynos_smp_prepare_cpus
,
232 .smp_secondary_init
= exynos_secondary_init
,
233 .smp_boot_secondary
= exynos_boot_secondary
,
234 #ifdef CONFIG_HOTPLUG_CPU
235 .cpu_die
= exynos_cpu_die
,