arch/arm/mach-exynos/platsmp.c

   1  /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   6  *
   7  *  Copyright (C) 2002 ARM Ltd.
   8  *  All Rights Reserved
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/smp_plat.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/firmware.h>
  28
  29 #include "common.h"
  30 #include "regs-pmu.h"
  31
  32 extern void exynos4_secondary_startup(void);
  33
  34 static inline void __iomem *cpu_boot_reg_base(void)
  35 {
  36         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
  37                 return S5P_INFORM5;
  38         return sysram_base_addr;
  39 }
  40
  41 static inline void __iomem *cpu_boot_reg(int cpu)
  42 {
  43         void __iomem *boot_reg;
  44
  45         boot_reg = cpu_boot_reg_base();
  46         if (!boot_reg)
  47                 return ERR_PTR(-ENODEV);
  48         if (soc_is_exynos4412())
  49                 boot_reg += 4*cpu;
  50         else if (soc_is_exynos5420() || soc_is_exynos5800())
  51                 boot_reg += 4;
  52         return boot_reg;
  53 }
  54
  55 /*
  56  * Write pen_release in a way that is guaranteed to be visible to all
  57  * observers, irrespective of whether they're taking part in coherency
  58  * or not.  This is necessary for the hotplug code to work reliably.
  59  */
  60 static void write_pen_release(int val)
  61 {
  62         pen_release = val;
  63         smp_wmb();
  64         sync_cache_w(&pen_release);
  65 }
  66
  67 static void __iomem *scu_base_addr(void)
  68 {
  69         return (void __iomem *)(S5P_VA_SCU);
  70 }
  71
  72 static DEFINE_SPINLOCK(boot_lock);
  73
  74 static void exynos_secondary_init(unsigned int cpu)
  75 {
  76         /*
  77          * let the primary processor know we're out of the
  78          * pen, then head off into the C entry point
  79          */
  80         write_pen_release(-1);
  81
  82         /*
  83          * Synchronise with the boot thread.
  84          */
  85         spin_lock(&boot_lock);
  86         spin_unlock(&boot_lock);
  87 }
  88
  89 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
  90 {
  91         unsigned long timeout;
  92         unsigned long phys_cpu = cpu_logical_map(cpu);
  93         int ret = -ENOSYS;
  94
  95         /*
  96          * Set synchronisation state between this boot processor
  97          * and the secondary one
  98          */
  99         spin_lock(&boot_lock);
 100
 101         /*
 102          * The secondary processor is waiting to be released from
 103          * the holding pen - release it, then wait for it to flag
 104          * that it has been released by resetting pen_release.
 105          *
 106          * Note that "pen_release" is the hardware CPU ID, whereas
 107          * "cpu" is Linux's internal ID.
 108          */
 109         write_pen_release(phys_cpu);
 110
 111         if (!exynos_cpu_power_state(cpu)) {
 112                 exynos_cpu_power_up(cpu);
 113                 timeout = 10;
 114
 115                 /* wait max 10 ms until cpu1 is on */
 116                 while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
 117                         if (timeout-- == 0)
 118                                 break;
 119
 120                         mdelay(1);
 121                 }
 122
 123                 if (timeout == 0) {
 124                         printk(KERN_ERR "cpu1 power enable failed");
 125                         spin_unlock(&boot_lock);
 126                         return -ETIMEDOUT;
 127                 }
 128         }
 129         /*
 130          * Send the secondary CPU a soft interrupt, thereby causing
 131          * the boot monitor to read the system wide flags register,
 132          * and branch to the address found there.
 133          */
 134
 135         timeout = jiffies + (1 * HZ);
 136         while (time_before(jiffies, timeout)) {
 137                 unsigned long boot_addr;
 138
 139                 smp_rmb();
 140
 141                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 142
 143                 /*
 144                  * Try to set boot address using firmware first
 145                  * and fall back to boot register if it fails.
 146                  */
 147                 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
 148                 if (ret && ret != -ENOSYS)
 149                         goto fail;
 150                 if (ret == -ENOSYS) {
 151                         void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
 152
 153                         if (IS_ERR(boot_reg)) {
 154                                 ret = PTR_ERR(boot_reg);
 155                                 goto fail;
 156                         }
 157                         __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
 158                 }
 159
 160                 call_firmware_op(cpu_boot, phys_cpu);
 161
 162                 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 163
 164                 if (pen_release == -1)
 165                         break;
 166
 167                 udelay(10);
 168         }
 169
 170         /*
 171          * now the secondary core is starting up let it run its
 172          * calibrations, then wait for it to finish
 173          */
 174 fail:
 175         spin_unlock(&boot_lock);
 176
 177         return pen_release != -1 ? ret : 0;
 178 }
 179
 180 /*
 181  * Initialise the CPU possible map early - this describes the CPUs
 182  * which may be present or become present in the system.
 183  */
 184
 185 static void __init exynos_smp_init_cpus(void)
 186 {
 187         void __iomem *scu_base = scu_base_addr();
 188         unsigned int i, ncores;
 189
 190         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 191                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 192         else
 193                 /*
 194                  * CPU Nodes are passed thru DT and set_cpu_possible
 195                  * is set by "arm_dt_init_cpu_maps".
 196                  */
 197                 return;
 198
 199         /* sanity check */
 200         if (ncores > nr_cpu_ids) {
 201                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 202                         ncores, nr_cpu_ids);
 203                 ncores = nr_cpu_ids;
 204         }
 205
 206         for (i = 0; i < ncores; i++)
 207                 set_cpu_possible(i, true);
 208 }
 209
 210 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 211 {
 212         int i;
 213
 214         exynos_sysram_init();
 215
 216         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 217                 scu_enable(scu_base_addr());
 218
 219         /*
 220          * Write the address of secondary startup into the
 221          * system-wide flags register. The boot monitor waits
 222          * until it receives a soft interrupt, and then the
 223          * secondary CPU branches to this address.
 224          *
 225          * Try using firmware operation first and fall back to
 226          * boot register if it fails.
 227          */
 228         for (i = 1; i < max_cpus; ++i) {
 229                 unsigned long phys_cpu;
 230                 unsigned long boot_addr;
 231                 int ret;
 232
 233                 phys_cpu = cpu_logical_map(i);
 234                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 235
 236                 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
 237                 if (ret && ret != -ENOSYS)
 238                         break;
 239                 if (ret == -ENOSYS) {
 240                         void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
 241
 242                         if (IS_ERR(boot_reg))
 243                                 break;
 244                         __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
 245                 }
 246         }
 247 }
 248
 249 struct smp_operations exynos_smp_ops __initdata = {
 250         .smp_init_cpus          = exynos_smp_init_cpus,
 251         .smp_prepare_cpus       = exynos_smp_prepare_cpus,
 252         .smp_secondary_init     = exynos_secondary_init,
 253         .smp_boot_secondary     = exynos_boot_secondary,
 254 #ifdef CONFIG_HOTPLUG_CPU
 255         .cpu_die                = exynos_cpu_die,
 256 #endif
 257 };