arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/suspend.h>
  29
  30 #include <plat/pm-common.h>
  31 #include <plat/regs-srom.h>
  32
  33 #include <mach/map.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37 #include "regs-sys.h"
  38
  39 /**
  40  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  41  * @hwirq: Hardware IRQ signal of the GIC
  42  * @mask: Mask in PMU wake-up mask register
  43  */
  44 struct exynos_wkup_irq {
  45         unsigned int hwirq;
  46         u32 mask;
  47 };
  48
  49 static struct sleep_save exynos5_sys_save[] = {
  50         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  51 };
  52
  53 static struct sleep_save exynos_core_save[] = {
  54         /* SROM side */
  55         SAVE_ITEM(S5P_SROM_BW),
  56         SAVE_ITEM(S5P_SROM_BC0),
  57         SAVE_ITEM(S5P_SROM_BC1),
  58         SAVE_ITEM(S5P_SROM_BC2),
  59         SAVE_ITEM(S5P_SROM_BC3),
  60 };
  61
  62 /*
  63  * GIC wake-up support
  64  */
  65
  66 static u32 exynos_irqwake_intmask = 0xffffffff;
  67
  68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  69         { 76, BIT(1) }, /* RTC alarm */
  70         { 77, BIT(2) }, /* RTC tick */
  71         { /* sentinel */ },
  72 };
  73
  74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  75         { 75, BIT(1) }, /* RTC alarm */
  76         { 76, BIT(2) }, /* RTC tick */
  77         { /* sentinel */ },
  78 };
  79
  80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  81 {
  82         const struct exynos_wkup_irq *wkup_irq;
  83
  84         if (soc_is_exynos5250())
  85                 wkup_irq = exynos5250_wkup_irq;
  86         else
  87                 wkup_irq = exynos4_wkup_irq;
  88
  89         while (wkup_irq->mask) {
  90                 if (wkup_irq->hwirq == data->hwirq) {
  91                         if (!state)
  92                                 exynos_irqwake_intmask |= wkup_irq->mask;
  93                         else
  94                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  95                         return 0;
  96                 }
  97                 ++wkup_irq;
  98         }
  99
 100         return -ENOENT;
 101 }
 102
 103 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 104                         pmu_base_addr + S5P_INFORM7 : \
 105                         (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 106                         (sysram_base_addr + 0x24) : \
 107                         pmu_base_addr + S5P_INFORM0))
 108 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 109                         pmu_base_addr + S5P_INFORM6 : \
 110                         (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 111                         (sysram_base_addr + 0x20) : \
 112                         pmu_base_addr + S5P_INFORM1))
 113
 114 #define S5P_CHECK_AFTR  0xFCBA0D10
 115 #define S5P_CHECK_SLEEP 0x00000BAD
 116
 117 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 118 static void exynos_set_wakeupmask(long mask)
 119 {
 120         pmu_raw_writel(mask, S5P_WAKEUP_MASK);
 121 }
 122
 123 static void exynos_cpu_set_boot_vector(long flags)
 124 {
 125         __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
 126         __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
 127 }
 128
 129 void exynos_enter_aftr(void)
 130 {
 131         exynos_set_wakeupmask(0x0000ff3e);
 132         exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 133         /* Set value of power down register for aftr mode */
 134         exynos_sys_powerdown_conf(SYS_AFTR);
 135 }
 136
 137 /* For Cortex-A9 Diagnostic and Power control register */
 138 static unsigned int save_arm_register[2];
 139
 140 static void exynos_cpu_save_register(void)
 141 {
 142         unsigned long tmp;
 143
 144         /* Save Power control register */
 145         asm ("mrc p15, 0, %0, c15, c0, 0"
 146              : "=r" (tmp) : : "cc");
 147
 148         save_arm_register[0] = tmp;
 149
 150         /* Save Diagnostic register */
 151         asm ("mrc p15, 0, %0, c15, c0, 1"
 152              : "=r" (tmp) : : "cc");
 153
 154         save_arm_register[1] = tmp;
 155 }
 156
 157 static void exynos_cpu_restore_register(void)
 158 {
 159         unsigned long tmp;
 160
 161         /* Restore Power control register */
 162         tmp = save_arm_register[0];
 163
 164         asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 165                       : : "r" (tmp)
 166                       : "cc");
 167
 168         /* Restore Diagnostic register */
 169         tmp = save_arm_register[1];
 170
 171         asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 172                       : : "r" (tmp)
 173                       : "cc");
 174 }
 175
 176 static int exynos_cpu_suspend(unsigned long arg)
 177 {
 178 #ifdef CONFIG_CACHE_L2X0
 179         outer_flush_all();
 180 #endif
 181
 182         if (soc_is_exynos5250())
 183                 flush_cache_all();
 184
 185         /* issue the standby signal into the pm unit. */
 186         cpu_do_idle();
 187
 188         pr_info("Failed to suspend the system\n");
 189         return 1; /* Aborting suspend */
 190 }
 191
 192 static void exynos_pm_prepare(void)
 193 {
 194         unsigned int tmp;
 195
 196         /* Set wake-up mask registers */
 197         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 198         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 199
 200         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 201
 202         if (soc_is_exynos5250()) {
 203                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 204                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 205                 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 206                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 207                 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 208         }
 209
 210         /* Set value of power down register for sleep mode */
 211
 212         exynos_sys_powerdown_conf(SYS_SLEEP);
 213         pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 214
 215         /* ensure at least INFORM0 has the resume address */
 216
 217         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 218 }
 219
 220 static void exynos_pm_central_suspend(void)
 221 {
 222         unsigned long tmp;
 223
 224         /* Setting Central Sequence Register for power down mode */
 225         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 226         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 227         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 228 }
 229
 230 static int exynos_pm_suspend(void)
 231 {
 232         unsigned long tmp;
 233
 234         exynos_pm_central_suspend();
 235
 236         /* Setting SEQ_OPTION register */
 237
 238         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 239         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 240
 241         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 242                 exynos_cpu_save_register();
 243
 244         return 0;
 245 }
 246
 247 static int exynos_pm_central_resume(void)
 248 {
 249         unsigned long tmp;
 250
 251         /*
 252          * If PMU failed while entering sleep mode, WFI will be
 253          * ignored by PMU and then exiting cpu_do_idle().
 254          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 255          * in this situation.
 256          */
 257         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 258         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 259                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 260                 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 261                 /* clear the wakeup state register */
 262                 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
 263                 /* No need to perform below restore code */
 264                 return -1;
 265         }
 266
 267         return 0;
 268 }
 269
 270 static void exynos_pm_resume(void)
 271 {
 272         if (exynos_pm_central_resume())
 273                 goto early_wakeup;
 274
 275         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 276                 exynos_cpu_restore_register();
 277
 278         /* For release retention */
 279
 280         pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 281         pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 282         pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 283         pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 284         pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 285         pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 286         pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 287
 288         if (soc_is_exynos5250())
 289                 s3c_pm_do_restore(exynos5_sys_save,
 290                         ARRAY_SIZE(exynos5_sys_save));
 291
 292         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 293
 294         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 295                 scu_enable(S5P_VA_SCU);
 296
 297 early_wakeup:
 298
 299         /* Clear SLEEP mode set in INFORM1 */
 300         pmu_raw_writel(0x0, S5P_INFORM1);
 301
 302         return;
 303 }
 304
 305 static struct syscore_ops exynos_pm_syscore_ops = {
 306         .suspend        = exynos_pm_suspend,
 307         .resume         = exynos_pm_resume,
 308 };
 309
 310 /*
 311  * Suspend Ops
 312  */
 313
 314 static int exynos_suspend_enter(suspend_state_t state)
 315 {
 316         int ret;
 317
 318         s3c_pm_debug_init();
 319
 320         S3C_PMDBG("%s: suspending the system...\n", __func__);
 321
 322         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 323                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 324
 325         if (exynos_irqwake_intmask == -1U
 326             && exynos_get_eint_wake_mask() == -1U) {
 327                 pr_err("%s: No wake-up sources!\n", __func__);
 328                 pr_err("%s: Aborting sleep\n", __func__);
 329                 return -EINVAL;
 330         }
 331
 332         s3c_pm_save_uarts();
 333         exynos_pm_prepare();
 334         flush_cache_all();
 335         s3c_pm_check_store();
 336
 337         ret = cpu_suspend(0, exynos_cpu_suspend);
 338         if (ret)
 339                 return ret;
 340
 341         s3c_pm_restore_uarts();
 342
 343         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 344                         pmu_raw_readl(S5P_WAKEUP_STAT));
 345
 346         s3c_pm_check_restore();
 347
 348         S3C_PMDBG("%s: resuming the system...\n", __func__);
 349
 350         return 0;
 351 }
 352
 353 static int exynos_suspend_prepare(void)
 354 {
 355         s3c_pm_check_prepare();
 356
 357         return 0;
 358 }
 359
 360 static void exynos_suspend_finish(void)
 361 {
 362         s3c_pm_check_cleanup();
 363 }
 364
 365 static const struct platform_suspend_ops exynos_suspend_ops = {
 366         .enter          = exynos_suspend_enter,
 367         .prepare        = exynos_suspend_prepare,
 368         .finish         = exynos_suspend_finish,
 369         .valid          = suspend_valid_only_mem,
 370 };
 371
 372 static int exynos_cpu_pm_notifier(struct notifier_block *self,
 373                                   unsigned long cmd, void *v)
 374 {
 375         int cpu = smp_processor_id();
 376
 377         switch (cmd) {
 378         case CPU_PM_ENTER:
 379                 if (cpu == 0) {
 380                         exynos_pm_central_suspend();
 381                         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 382                                 exynos_cpu_save_register();
 383                 }
 384                 break;
 385
 386         case CPU_PM_EXIT:
 387                 if (cpu == 0) {
 388                         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 389                                 scu_enable(S5P_VA_SCU);
 390                                 exynos_cpu_restore_register();
 391                         }
 392                         exynos_pm_central_resume();
 393                 }
 394                 break;
 395         }
 396
 397         return NOTIFY_OK;
 398 }
 399
 400 static struct notifier_block exynos_cpu_pm_notifier_block = {
 401         .notifier_call = exynos_cpu_pm_notifier,
 402 };
 403
 404 void __init exynos_pm_init(void)
 405 {
 406         u32 tmp;
 407
 408         cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
 409
 410         /* Platform-specific GIC callback */
 411         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 412
 413         /* All wakeup disable */
 414         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 415         tmp |= ((0xFF << 8) | (0x1F << 1));
 416         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 417
 418         register_syscore_ops(&exynos_pm_syscore_ops);
 419         suspend_set_ops(&exynos_suspend_ops);
 420 }