arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/suspend.h>
  29
  30 #include <plat/pm-common.h>
  31 #include <plat/pll.h>
  32 #include <plat/regs-srom.h>
  33
  34 #include <mach/map.h>
  35
  36 #include "common.h"
  37 #include "regs-pmu.h"
  38 #include "regs-sys.h"
  39
  40 /**
  41  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  42  * @hwirq: Hardware IRQ signal of the GIC
  43  * @mask: Mask in PMU wake-up mask register
  44  */
  45 struct exynos_wkup_irq {
  46         unsigned int hwirq;
  47         u32 mask;
  48 };
  49
  50 static struct sleep_save exynos5_sys_save[] = {
  51         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  52 };
  53
  54 static struct sleep_save exynos_core_save[] = {
  55         /* SROM side */
  56         SAVE_ITEM(S5P_SROM_BW),
  57         SAVE_ITEM(S5P_SROM_BC0),
  58         SAVE_ITEM(S5P_SROM_BC1),
  59         SAVE_ITEM(S5P_SROM_BC2),
  60         SAVE_ITEM(S5P_SROM_BC3),
  61 };
  62
  63 /*
  64  * GIC wake-up support
  65  */
  66
  67 static u32 exynos_irqwake_intmask = 0xffffffff;
  68
  69 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  70         { 76, BIT(1) }, /* RTC alarm */
  71         { 77, BIT(2) }, /* RTC tick */
  72         { /* sentinel */ },
  73 };
  74
  75 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  76         { 75, BIT(1) }, /* RTC alarm */
  77         { 76, BIT(2) }, /* RTC tick */
  78         { /* sentinel */ },
  79 };
  80
  81 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  82 {
  83         const struct exynos_wkup_irq *wkup_irq;
  84
  85         if (soc_is_exynos5250())
  86                 wkup_irq = exynos5250_wkup_irq;
  87         else
  88                 wkup_irq = exynos4_wkup_irq;
  89
  90         while (wkup_irq->mask) {
  91                 if (wkup_irq->hwirq == data->hwirq) {
  92                         if (!state)
  93                                 exynos_irqwake_intmask |= wkup_irq->mask;
  94                         else
  95                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  96                         return 0;
  97                 }
  98                 ++wkup_irq;
  99         }
 100
 101         return -ENOENT;
 102 }
 103
 104 /**
 105  * exynos_core_power_down : power down the specified cpu
 106  * @cpu : the cpu to power down
 107  *
 108  * Power down the specified cpu. The sequence must be finished by a
 109  * call to cpu_do_idle()
 110  *
 111  */
 112 void exynos_cpu_power_down(int cpu)
 113 {
 114         pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 115 }
 116
 117 /**
 118  * exynos_cpu_power_up : power up the specified cpu
 119  * @cpu : the cpu to power up
 120  *
 121  * Power up the specified cpu
 122  */
 123 void exynos_cpu_power_up(int cpu)
 124 {
 125         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 126                         EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 127 }
 128
 129 /**
 130  * exynos_cpu_power_state : returns the power state of the cpu
 131  * @cpu : the cpu to retrieve the power state from
 132  *
 133  */
 134 int exynos_cpu_power_state(int cpu)
 135 {
 136         return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
 137                         S5P_CORE_LOCAL_PWR_EN);
 138 }
 139
 140 /**
 141  * exynos_cluster_power_down : power down the specified cluster
 142  * @cluster : the cluster to power down
 143  */
 144 void exynos_cluster_power_down(int cluster)
 145 {
 146         pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
 147 }
 148
 149 /**
 150  * exynos_cluster_power_up : power up the specified cluster
 151  * @cluster : the cluster to power up
 152  */
 153 void exynos_cluster_power_up(int cluster)
 154 {
 155         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 156                         EXYNOS_COMMON_CONFIGURATION(cluster));
 157 }
 158
 159 /**
 160  * exynos_cluster_power_state : returns the power state of the cluster
 161  * @cluster : the cluster to retrieve the power state from
 162  *
 163  */
 164 int exynos_cluster_power_state(int cluster)
 165 {
 166         return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
 167                         S5P_CORE_LOCAL_PWR_EN);
 168 }
 169
 170 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 171                         pmu_base_addr + S5P_INFORM7 : \
 172                         (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 173                         (sysram_base_addr + 0x24) : \
 174                         pmu_base_addr + S5P_INFORM0))
 175 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 176                         pmu_base_addr + S5P_INFORM6 : \
 177                         (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 178                         (sysram_base_addr + 0x20) : \
 179                         pmu_base_addr + S5P_INFORM1))
 180
 181 #define S5P_CHECK_AFTR  0xFCBA0D10
 182 #define S5P_CHECK_SLEEP 0x00000BAD
 183
 184 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 185 static void exynos_set_wakeupmask(long mask)
 186 {
 187         pmu_raw_writel(mask, S5P_WAKEUP_MASK);
 188 }
 189
 190 static void exynos_cpu_set_boot_vector(long flags)
 191 {
 192         __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
 193         __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
 194 }
 195
 196 void exynos_enter_aftr(void)
 197 {
 198         exynos_set_wakeupmask(0x0000ff3e);
 199         exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 200         /* Set value of power down register for aftr mode */
 201         exynos_sys_powerdown_conf(SYS_AFTR);
 202 }
 203
 204 /* For Cortex-A9 Diagnostic and Power control register */
 205 static unsigned int save_arm_register[2];
 206
 207 static void exynos_cpu_save_register(void)
 208 {
 209         unsigned long tmp;
 210
 211         /* Save Power control register */
 212         asm ("mrc p15, 0, %0, c15, c0, 0"
 213              : "=r" (tmp) : : "cc");
 214
 215         save_arm_register[0] = tmp;
 216
 217         /* Save Diagnostic register */
 218         asm ("mrc p15, 0, %0, c15, c0, 1"
 219              : "=r" (tmp) : : "cc");
 220
 221         save_arm_register[1] = tmp;
 222 }
 223
 224 static void exynos_cpu_restore_register(void)
 225 {
 226         unsigned long tmp;
 227
 228         /* Restore Power control register */
 229         tmp = save_arm_register[0];
 230
 231         asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 232                       : : "r" (tmp)
 233                       : "cc");
 234
 235         /* Restore Diagnostic register */
 236         tmp = save_arm_register[1];
 237
 238         asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 239                       : : "r" (tmp)
 240                       : "cc");
 241 }
 242
 243 static int exynos_cpu_suspend(unsigned long arg)
 244 {
 245 #ifdef CONFIG_CACHE_L2X0
 246         outer_flush_all();
 247 #endif
 248
 249         if (soc_is_exynos5250())
 250                 flush_cache_all();
 251
 252         /* issue the standby signal into the pm unit. */
 253         cpu_do_idle();
 254
 255         pr_info("Failed to suspend the system\n");
 256         return 1; /* Aborting suspend */
 257 }
 258
 259 static void exynos_pm_prepare(void)
 260 {
 261         unsigned int tmp;
 262
 263         /* Set wake-up mask registers */
 264         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 265         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 266
 267         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 268
 269         if (soc_is_exynos5250()) {
 270                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 271                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 272                 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 273                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 274                 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 275         }
 276
 277         /* Set value of power down register for sleep mode */
 278
 279         exynos_sys_powerdown_conf(SYS_SLEEP);
 280         pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 281
 282         /* ensure at least INFORM0 has the resume address */
 283
 284         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 285 }
 286
 287 static void exynos_pm_central_suspend(void)
 288 {
 289         unsigned long tmp;
 290
 291         /* Setting Central Sequence Register for power down mode */
 292         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 293         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 294         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 295 }
 296
 297 static int exynos_pm_suspend(void)
 298 {
 299         unsigned long tmp;
 300
 301         exynos_pm_central_suspend();
 302
 303         /* Setting SEQ_OPTION register */
 304
 305         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 306         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 307
 308         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 309                 exynos_cpu_save_register();
 310
 311         return 0;
 312 }
 313
 314 static int exynos_pm_central_resume(void)
 315 {
 316         unsigned long tmp;
 317
 318         /*
 319          * If PMU failed while entering sleep mode, WFI will be
 320          * ignored by PMU and then exiting cpu_do_idle().
 321          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 322          * in this situation.
 323          */
 324         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 325         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 326                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 327                 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 328                 /* clear the wakeup state register */
 329                 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
 330                 /* No need to perform below restore code */
 331                 return -1;
 332         }
 333
 334         return 0;
 335 }
 336
 337 static void exynos_pm_resume(void)
 338 {
 339         if (exynos_pm_central_resume())
 340                 goto early_wakeup;
 341
 342         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 343                 exynos_cpu_restore_register();
 344
 345         /* For release retention */
 346
 347         pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 348         pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 349         pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 350         pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 351         pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 352         pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 353         pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 354
 355         if (soc_is_exynos5250())
 356                 s3c_pm_do_restore(exynos5_sys_save,
 357                         ARRAY_SIZE(exynos5_sys_save));
 358
 359         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 360
 361         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 362                 scu_enable(S5P_VA_SCU);
 363
 364 early_wakeup:
 365
 366         /* Clear SLEEP mode set in INFORM1 */
 367         pmu_raw_writel(0x0, S5P_INFORM1);
 368
 369         return;
 370 }
 371
 372 static struct syscore_ops exynos_pm_syscore_ops = {
 373         .suspend        = exynos_pm_suspend,
 374         .resume         = exynos_pm_resume,
 375 };
 376
 377 /*
 378  * Suspend Ops
 379  */
 380
 381 static int exynos_suspend_enter(suspend_state_t state)
 382 {
 383         int ret;
 384
 385         s3c_pm_debug_init();
 386
 387         S3C_PMDBG("%s: suspending the system...\n", __func__);
 388
 389         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 390                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 391
 392         if (exynos_irqwake_intmask == -1U
 393             && exynos_get_eint_wake_mask() == -1U) {
 394                 pr_err("%s: No wake-up sources!\n", __func__);
 395                 pr_err("%s: Aborting sleep\n", __func__);
 396                 return -EINVAL;
 397         }
 398
 399         s3c_pm_save_uarts();
 400         exynos_pm_prepare();
 401         flush_cache_all();
 402         s3c_pm_check_store();
 403
 404         ret = cpu_suspend(0, exynos_cpu_suspend);
 405         if (ret)
 406                 return ret;
 407
 408         s3c_pm_restore_uarts();
 409
 410         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 411                         pmu_raw_readl(S5P_WAKEUP_STAT));
 412
 413         s3c_pm_check_restore();
 414
 415         S3C_PMDBG("%s: resuming the system...\n", __func__);
 416
 417         return 0;
 418 }
 419
 420 static int exynos_suspend_prepare(void)
 421 {
 422         s3c_pm_check_prepare();
 423
 424         return 0;
 425 }
 426
 427 static void exynos_suspend_finish(void)
 428 {
 429         s3c_pm_check_cleanup();
 430 }
 431
 432 static const struct platform_suspend_ops exynos_suspend_ops = {
 433         .enter          = exynos_suspend_enter,
 434         .prepare        = exynos_suspend_prepare,
 435         .finish         = exynos_suspend_finish,
 436         .valid          = suspend_valid_only_mem,
 437 };
 438
 439 static int exynos_cpu_pm_notifier(struct notifier_block *self,
 440                                   unsigned long cmd, void *v)
 441 {
 442         int cpu = smp_processor_id();
 443
 444         switch (cmd) {
 445         case CPU_PM_ENTER:
 446                 if (cpu == 0) {
 447                         exynos_pm_central_suspend();
 448                         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 449                                 exynos_cpu_save_register();
 450                 }
 451                 break;
 452
 453         case CPU_PM_EXIT:
 454                 if (cpu == 0) {
 455                         if (read_cpuid_part_number() ==
 456                                         ARM_CPU_PART_CORTEX_A9) {
 457                                 scu_enable(S5P_VA_SCU);
 458                                 exynos_cpu_restore_register();
 459                         }
 460                         exynos_pm_central_resume();
 461                 }
 462                 break;
 463         }
 464
 465         return NOTIFY_OK;
 466 }
 467
 468 static struct notifier_block exynos_cpu_pm_notifier_block = {
 469         .notifier_call = exynos_cpu_pm_notifier,
 470 };
 471
 472 void __init exynos_pm_init(void)
 473 {
 474         u32 tmp;
 475
 476         cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
 477
 478         /* Platform-specific GIC callback */
 479         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 480
 481         /* All wakeup disable */
 482         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 483         tmp |= ((0xFF << 8) | (0x1F << 1));
 484         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 485
 486         register_syscore_ops(&exynos_pm_syscore_ops);
 487         suspend_set_ops(&exynos_suspend_ops);
 488 }