arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/suspend.h>
  29
  30 #include <plat/pm-common.h>
  31 #include <plat/regs-srom.h>
  32
  33 #include <mach/map.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37 #include "regs-sys.h"
  38
  39 /**
  40  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  41  * @hwirq: Hardware IRQ signal of the GIC
  42  * @mask: Mask in PMU wake-up mask register
  43  */
  44 struct exynos_wkup_irq {
  45         unsigned int hwirq;
  46         u32 mask;
  47 };
  48
  49 static struct sleep_save exynos5_sys_save[] = {
  50         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  51 };
  52
  53 static struct sleep_save exynos_core_save[] = {
  54         /* SROM side */
  55         SAVE_ITEM(S5P_SROM_BW),
  56         SAVE_ITEM(S5P_SROM_BC0),
  57         SAVE_ITEM(S5P_SROM_BC1),
  58         SAVE_ITEM(S5P_SROM_BC2),
  59         SAVE_ITEM(S5P_SROM_BC3),
  60 };
  61
  62 /*
  63  * GIC wake-up support
  64  */
  65
  66 static u32 exynos_irqwake_intmask = 0xffffffff;
  67
  68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  69         { 76, BIT(1) }, /* RTC alarm */
  70         { 77, BIT(2) }, /* RTC tick */
  71         { /* sentinel */ },
  72 };
  73
  74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  75         { 75, BIT(1) }, /* RTC alarm */
  76         { 76, BIT(2) }, /* RTC tick */
  77         { /* sentinel */ },
  78 };
  79
  80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  81 {
  82         const struct exynos_wkup_irq *wkup_irq;
  83
  84         if (soc_is_exynos5250())
  85                 wkup_irq = exynos5250_wkup_irq;
  86         else
  87                 wkup_irq = exynos4_wkup_irq;
  88
  89         while (wkup_irq->mask) {
  90                 if (wkup_irq->hwirq == data->hwirq) {
  91                         if (!state)
  92                                 exynos_irqwake_intmask |= wkup_irq->mask;
  93                         else
  94                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
  95                         return 0;
  96                 }
  97                 ++wkup_irq;
  98         }
  99
 100         return -ENOENT;
 101 }
 102
 103 /**
 104  * exynos_core_power_down : power down the specified cpu
 105  * @cpu : the cpu to power down
 106  *
 107  * Power down the specified cpu. The sequence must be finished by a
 108  * call to cpu_do_idle()
 109  *
 110  */
 111 void exynos_cpu_power_down(int cpu)
 112 {
 113         pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 114 }
 115
 116 /**
 117  * exynos_cpu_power_up : power up the specified cpu
 118  * @cpu : the cpu to power up
 119  *
 120  * Power up the specified cpu
 121  */
 122 void exynos_cpu_power_up(int cpu)
 123 {
 124         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 125                         EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 126 }
 127
 128 /**
 129  * exynos_cpu_power_state : returns the power state of the cpu
 130  * @cpu : the cpu to retrieve the power state from
 131  *
 132  */
 133 int exynos_cpu_power_state(int cpu)
 134 {
 135         return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
 136                         S5P_CORE_LOCAL_PWR_EN);
 137 }
 138
 139 /**
 140  * exynos_cluster_power_down : power down the specified cluster
 141  * @cluster : the cluster to power down
 142  */
 143 void exynos_cluster_power_down(int cluster)
 144 {
 145         pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
 146 }
 147
 148 /**
 149  * exynos_cluster_power_up : power up the specified cluster
 150  * @cluster : the cluster to power up
 151  */
 152 void exynos_cluster_power_up(int cluster)
 153 {
 154         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 155                         EXYNOS_COMMON_CONFIGURATION(cluster));
 156 }
 157
 158 /**
 159  * exynos_cluster_power_state : returns the power state of the cluster
 160  * @cluster : the cluster to retrieve the power state from
 161  *
 162  */
 163 int exynos_cluster_power_state(int cluster)
 164 {
 165         return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
 166                         S5P_CORE_LOCAL_PWR_EN);
 167 }
 168
 169 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 170                         pmu_base_addr + S5P_INFORM7 : \
 171                         (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 172                         (sysram_base_addr + 0x24) : \
 173                         pmu_base_addr + S5P_INFORM0))
 174 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
 175                         pmu_base_addr + S5P_INFORM6 : \
 176                         (samsung_rev() == EXYNOS4210_REV_1_0 ? \
 177                         (sysram_base_addr + 0x20) : \
 178                         pmu_base_addr + S5P_INFORM1))
 179
 180 #define S5P_CHECK_AFTR  0xFCBA0D10
 181 #define S5P_CHECK_SLEEP 0x00000BAD
 182
 183 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 184 static void exynos_set_wakeupmask(long mask)
 185 {
 186         pmu_raw_writel(mask, S5P_WAKEUP_MASK);
 187 }
 188
 189 static void exynos_cpu_set_boot_vector(long flags)
 190 {
 191         __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
 192         __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
 193 }
 194
 195 void exynos_enter_aftr(void)
 196 {
 197         exynos_set_wakeupmask(0x0000ff3e);
 198         exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 199         /* Set value of power down register for aftr mode */
 200         exynos_sys_powerdown_conf(SYS_AFTR);
 201 }
 202
 203 /* For Cortex-A9 Diagnostic and Power control register */
 204 static unsigned int save_arm_register[2];
 205
 206 static void exynos_cpu_save_register(void)
 207 {
 208         unsigned long tmp;
 209
 210         /* Save Power control register */
 211         asm ("mrc p15, 0, %0, c15, c0, 0"
 212              : "=r" (tmp) : : "cc");
 213
 214         save_arm_register[0] = tmp;
 215
 216         /* Save Diagnostic register */
 217         asm ("mrc p15, 0, %0, c15, c0, 1"
 218              : "=r" (tmp) : : "cc");
 219
 220         save_arm_register[1] = tmp;
 221 }
 222
 223 static void exynos_cpu_restore_register(void)
 224 {
 225         unsigned long tmp;
 226
 227         /* Restore Power control register */
 228         tmp = save_arm_register[0];
 229
 230         asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 231                       : : "r" (tmp)
 232                       : "cc");
 233
 234         /* Restore Diagnostic register */
 235         tmp = save_arm_register[1];
 236
 237         asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 238                       : : "r" (tmp)
 239                       : "cc");
 240 }
 241
 242 static int exynos_cpu_suspend(unsigned long arg)
 243 {
 244 #ifdef CONFIG_CACHE_L2X0
 245         outer_flush_all();
 246 #endif
 247
 248         if (soc_is_exynos5250())
 249                 flush_cache_all();
 250
 251         /* issue the standby signal into the pm unit. */
 252         cpu_do_idle();
 253
 254         pr_info("Failed to suspend the system\n");
 255         return 1; /* Aborting suspend */
 256 }
 257
 258 static void exynos_pm_prepare(void)
 259 {
 260         unsigned int tmp;
 261
 262         /* Set wake-up mask registers */
 263         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 264         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 265
 266         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 267
 268         if (soc_is_exynos5250()) {
 269                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 270                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 271                 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 272                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 273                 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 274         }
 275
 276         /* Set value of power down register for sleep mode */
 277
 278         exynos_sys_powerdown_conf(SYS_SLEEP);
 279         pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 280
 281         /* ensure at least INFORM0 has the resume address */
 282
 283         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 284 }
 285
 286 static void exynos_pm_central_suspend(void)
 287 {
 288         unsigned long tmp;
 289
 290         /* Setting Central Sequence Register for power down mode */
 291         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 292         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 293         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 294 }
 295
 296 static int exynos_pm_suspend(void)
 297 {
 298         unsigned long tmp;
 299
 300         exynos_pm_central_suspend();
 301
 302         /* Setting SEQ_OPTION register */
 303
 304         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 305         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 306
 307         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 308                 exynos_cpu_save_register();
 309
 310         return 0;
 311 }
 312
 313 static int exynos_pm_central_resume(void)
 314 {
 315         unsigned long tmp;
 316
 317         /*
 318          * If PMU failed while entering sleep mode, WFI will be
 319          * ignored by PMU and then exiting cpu_do_idle().
 320          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 321          * in this situation.
 322          */
 323         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 324         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 325                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 326                 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 327                 /* clear the wakeup state register */
 328                 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
 329                 /* No need to perform below restore code */
 330                 return -1;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static void exynos_pm_resume(void)
 337 {
 338         if (exynos_pm_central_resume())
 339                 goto early_wakeup;
 340
 341         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 342                 exynos_cpu_restore_register();
 343
 344         /* For release retention */
 345
 346         pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 347         pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 348         pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 349         pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 350         pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 351         pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 352         pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 353
 354         if (soc_is_exynos5250())
 355                 s3c_pm_do_restore(exynos5_sys_save,
 356                         ARRAY_SIZE(exynos5_sys_save));
 357
 358         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 359
 360         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 361                 scu_enable(S5P_VA_SCU);
 362
 363 early_wakeup:
 364
 365         /* Clear SLEEP mode set in INFORM1 */
 366         pmu_raw_writel(0x0, S5P_INFORM1);
 367
 368         return;
 369 }
 370
 371 static struct syscore_ops exynos_pm_syscore_ops = {
 372         .suspend        = exynos_pm_suspend,
 373         .resume         = exynos_pm_resume,
 374 };
 375
 376 /*
 377  * Suspend Ops
 378  */
 379
 380 static int exynos_suspend_enter(suspend_state_t state)
 381 {
 382         int ret;
 383
 384         s3c_pm_debug_init();
 385
 386         S3C_PMDBG("%s: suspending the system...\n", __func__);
 387
 388         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 389                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 390
 391         if (exynos_irqwake_intmask == -1U
 392             && exynos_get_eint_wake_mask() == -1U) {
 393                 pr_err("%s: No wake-up sources!\n", __func__);
 394                 pr_err("%s: Aborting sleep\n", __func__);
 395                 return -EINVAL;
 396         }
 397
 398         s3c_pm_save_uarts();
 399         exynos_pm_prepare();
 400         flush_cache_all();
 401         s3c_pm_check_store();
 402
 403         ret = cpu_suspend(0, exynos_cpu_suspend);
 404         if (ret)
 405                 return ret;
 406
 407         s3c_pm_restore_uarts();
 408
 409         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 410                         pmu_raw_readl(S5P_WAKEUP_STAT));
 411
 412         s3c_pm_check_restore();
 413
 414         S3C_PMDBG("%s: resuming the system...\n", __func__);
 415
 416         return 0;
 417 }
 418
 419 static int exynos_suspend_prepare(void)
 420 {
 421         s3c_pm_check_prepare();
 422
 423         return 0;
 424 }
 425
 426 static void exynos_suspend_finish(void)
 427 {
 428         s3c_pm_check_cleanup();
 429 }
 430
 431 static const struct platform_suspend_ops exynos_suspend_ops = {
 432         .enter          = exynos_suspend_enter,
 433         .prepare        = exynos_suspend_prepare,
 434         .finish         = exynos_suspend_finish,
 435         .valid          = suspend_valid_only_mem,
 436 };
 437
 438 static int exynos_cpu_pm_notifier(struct notifier_block *self,
 439                                   unsigned long cmd, void *v)
 440 {
 441         int cpu = smp_processor_id();
 442
 443         switch (cmd) {
 444         case CPU_PM_ENTER:
 445                 if (cpu == 0) {
 446                         exynos_pm_central_suspend();
 447                         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
 448                                 exynos_cpu_save_register();
 449                 }
 450                 break;
 451
 452         case CPU_PM_EXIT:
 453                 if (cpu == 0) {
 454                         if (read_cpuid_part_number() ==
 455                                         ARM_CPU_PART_CORTEX_A9) {
 456                                 scu_enable(S5P_VA_SCU);
 457                                 exynos_cpu_restore_register();
 458                         }
 459                         exynos_pm_central_resume();
 460                 }
 461                 break;
 462         }
 463
 464         return NOTIFY_OK;
 465 }
 466
 467 static struct notifier_block exynos_cpu_pm_notifier_block = {
 468         .notifier_call = exynos_cpu_pm_notifier,
 469 };
 470
 471 void __init exynos_pm_init(void)
 472 {
 473         u32 tmp;
 474
 475         cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
 476
 477         /* Platform-specific GIC callback */
 478         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 479
 480         /* All wakeup disable */
 481         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 482         tmp |= ((0xFF << 8) | (0x1F << 1));
 483         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 484
 485         register_syscore_ops(&exynos_pm_syscore_ops);
 486         suspend_set_ops(&exynos_suspend_ops);
 487 }