arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <plat/cpu.h>
  28 #include <plat/pm.h>
  29 #include <plat/pll.h>
  30 #include <plat/regs-srom.h>
  31
  32 #include <mach/regs-irq.h>
  33 #include <mach/regs-gpio.h>
  34 #include <mach/regs-clock.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/pm-core.h>
  37
  38 #include "common.h"
  39
  40 static struct sleep_save exynos4_set_clksrc[] = {
  41         { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
  42         { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
  43         { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
  44         { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
  45         { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
  46         { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
  47         { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
  48         { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
  49         { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
  50 };
  51
  52 static struct sleep_save exynos4210_set_clksrc[] = {
  53         { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
  54 };
  55
  56 static struct sleep_save exynos4_epll_save[] = {
  57         SAVE_ITEM(EXYNOS4_EPLL_CON0),
  58         SAVE_ITEM(EXYNOS4_EPLL_CON1),
  59 };
  60
  61 static struct sleep_save exynos4_vpll_save[] = {
  62         SAVE_ITEM(EXYNOS4_VPLL_CON0),
  63         SAVE_ITEM(EXYNOS4_VPLL_CON1),
  64 };
  65
  66 static struct sleep_save exynos5_sys_save[] = {
  67         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  68 };
  69
  70 static struct sleep_save exynos_core_save[] = {
  71         /* SROM side */
  72         SAVE_ITEM(S5P_SROM_BW),
  73         SAVE_ITEM(S5P_SROM_BC0),
  74         SAVE_ITEM(S5P_SROM_BC1),
  75         SAVE_ITEM(S5P_SROM_BC2),
  76         SAVE_ITEM(S5P_SROM_BC3),
  77 };
  78
  79
  80 /* For Cortex-A9 Diagnostic and Power control register */
  81 static unsigned int save_arm_register[2];
  82
  83 static int exynos_cpu_suspend(unsigned long arg)
  84 {
  85 #ifdef CONFIG_CACHE_L2X0
  86         outer_flush_all();
  87 #endif
  88
  89         if (soc_is_exynos5250())
  90                 flush_cache_all();
  91
  92         /* issue the standby signal into the pm unit. */
  93         cpu_do_idle();
  94
  95         pr_info("Failed to suspend the system\n");
  96         return 1; /* Aborting suspend */
  97 }
  98
  99 static void exynos_pm_prepare(void)
 100 {
 101         unsigned int tmp;
 102
 103         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 104
 105         if (!soc_is_exynos5250()) {
 106                 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
 107                 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 108         } else {
 109                 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
 110                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 111                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 112                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 113                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 114         }
 115
 116         /* Set value of power down register for sleep mode */
 117
 118         exynos_sys_powerdown_conf(SYS_SLEEP);
 119         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 120
 121         /* ensure at least INFORM0 has the resume address */
 122
 123         __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
 124
 125         /* Before enter central sequence mode, clock src register have to set */
 126
 127         if (!soc_is_exynos5250())
 128                 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 129
 130         if (soc_is_exynos4210())
 131                 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
 132
 133 }
 134
 135 static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
 136 {
 137         pm_cpu_prep = exynos_pm_prepare;
 138         pm_cpu_sleep = exynos_cpu_suspend;
 139
 140         return 0;
 141 }
 142
 143 static unsigned long pll_base_rate;
 144
 145 static void exynos4_restore_pll(void)
 146 {
 147         unsigned long pll_con, locktime, lockcnt;
 148         unsigned long pll_in_rate;
 149         unsigned int p_div, epll_wait = 0, vpll_wait = 0;
 150
 151         if (pll_base_rate == 0)
 152                 return;
 153
 154         pll_in_rate = pll_base_rate;
 155
 156         /* EPLL */
 157         pll_con = exynos4_epll_save[0].val;
 158
 159         if (pll_con & (1 << 31)) {
 160                 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
 161                 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
 162
 163                 pll_in_rate /= 1000000;
 164
 165                 locktime = (3000 / pll_in_rate) * p_div;
 166                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 167
 168                 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 169
 170                 s3c_pm_do_restore_core(exynos4_epll_save,
 171                                         ARRAY_SIZE(exynos4_epll_save));
 172                 epll_wait = 1;
 173         }
 174
 175         pll_in_rate = pll_base_rate;
 176
 177         /* VPLL */
 178         pll_con = exynos4_vpll_save[0].val;
 179
 180         if (pll_con & (1 << 31)) {
 181                 pll_in_rate /= 1000000;
 182                 /* 750us */
 183                 locktime = 750;
 184                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 185
 186                 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 187
 188                 s3c_pm_do_restore_core(exynos4_vpll_save,
 189                                         ARRAY_SIZE(exynos4_vpll_save));
 190                 vpll_wait = 1;
 191         }
 192
 193         /* Wait PLL locking */
 194
 195         do {
 196                 if (epll_wait) {
 197                         pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
 198                         if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
 199                                 epll_wait = 0;
 200                 }
 201
 202                 if (vpll_wait) {
 203                         pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
 204                         if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
 205                                 vpll_wait = 0;
 206                 }
 207         } while (epll_wait || vpll_wait);
 208 }
 209
 210 static struct subsys_interface exynos_pm_interface = {
 211         .name           = "exynos_pm",
 212         .subsys         = &exynos_subsys,
 213         .add_dev        = exynos_pm_add,
 214 };
 215
 216 static __init int exynos_pm_drvinit(void)
 217 {
 218         struct clk *pll_base;
 219         unsigned int tmp;
 220
 221         s3c_pm_init();
 222
 223         /* All wakeup disable */
 224
 225         tmp = __raw_readl(S5P_WAKEUP_MASK);
 226         tmp |= ((0xFF << 8) | (0x1F << 1));
 227         __raw_writel(tmp, S5P_WAKEUP_MASK);
 228
 229         if (!soc_is_exynos5250()) {
 230                 pll_base = clk_get(NULL, "xtal");
 231
 232                 if (!IS_ERR(pll_base)) {
 233                         pll_base_rate = clk_get_rate(pll_base);
 234                         clk_put(pll_base);
 235                 }
 236         }
 237
 238         return subsys_interface_register(&exynos_pm_interface);
 239 }
 240 arch_initcall(exynos_pm_drvinit);
 241
 242 static int exynos_pm_suspend(void)
 243 {
 244         unsigned long tmp;
 245
 246         /* Setting Central Sequence Register for power down mode */
 247
 248         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 249         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 250         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 251
 252         /* Setting SEQ_OPTION register */
 253
 254         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 255         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 256
 257         if (!soc_is_exynos5250()) {
 258                 /* Save Power control register */
 259                 asm ("mrc p15, 0, %0, c15, c0, 0"
 260                      : "=r" (tmp) : : "cc");
 261                 save_arm_register[0] = tmp;
 262
 263                 /* Save Diagnostic register */
 264                 asm ("mrc p15, 0, %0, c15, c0, 1"
 265                      : "=r" (tmp) : : "cc");
 266                 save_arm_register[1] = tmp;
 267         }
 268
 269         return 0;
 270 }
 271
 272 static void exynos_pm_resume(void)
 273 {
 274         unsigned long tmp;
 275
 276         /*
 277          * If PMU failed while entering sleep mode, WFI will be
 278          * ignored by PMU and then exiting cpu_do_idle().
 279          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 280          * in this situation.
 281          */
 282         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 283         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 284                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 285                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 286                 /* clear the wakeup state register */
 287                 __raw_writel(0x0, S5P_WAKEUP_STAT);
 288                 /* No need to perform below restore code */
 289                 goto early_wakeup;
 290         }
 291         if (!soc_is_exynos5250()) {
 292                 /* Restore Power control register */
 293                 tmp = save_arm_register[0];
 294                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 295                               : : "r" (tmp)
 296                               : "cc");
 297
 298                 /* Restore Diagnostic register */
 299                 tmp = save_arm_register[1];
 300                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 301                               : : "r" (tmp)
 302                               : "cc");
 303         }
 304
 305         /* For release retention */
 306
 307         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 308         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 309         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 310         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 311         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 312         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 313         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 314
 315         if (soc_is_exynos5250())
 316                 s3c_pm_do_restore(exynos5_sys_save,
 317                         ARRAY_SIZE(exynos5_sys_save));
 318
 319         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 320
 321         if (!soc_is_exynos5250()) {
 322                 exynos4_restore_pll();
 323
 324 #ifdef CONFIG_SMP
 325                 scu_enable(S5P_VA_SCU);
 326 #endif
 327         }
 328
 329 early_wakeup:
 330
 331         /* Clear SLEEP mode set in INFORM1 */
 332         __raw_writel(0x0, S5P_INFORM1);
 333
 334         return;
 335 }
 336
 337 static struct syscore_ops exynos_pm_syscore_ops = {
 338         .suspend        = exynos_pm_suspend,
 339         .resume         = exynos_pm_resume,
 340 };
 341
 342 static __init int exynos_pm_syscore_init(void)
 343 {
 344         register_syscore_ops(&exynos_pm_syscore_ops);
 345         return 0;
 346 }
 347 arch_initcall(exynos_pm_syscore_init);