2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Suspend support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irqchip/arm-gic.h>
22 #include <linux/err.h>
23 #include <linux/regulator/machine.h>
25 #include <asm/cacheflush.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/firmware.h>
29 #include <asm/smp_scu.h>
30 #include <asm/suspend.h>
32 #include <plat/pm-common.h>
33 #include <plat/regs-srom.h>
37 #include "exynos-pmu.h"
39 #define S5P_CHECK_SLEEP 0x00000BAD
41 #define REG_TABLE_END (-1U)
43 #define EXYNOS5420_CPU_STATE 0x28
46 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
47 * @hwirq: Hardware IRQ signal of the GIC
48 * @mask: Mask in PMU wake-up mask register
50 struct exynos_wkup_irq
{
55 static struct sleep_save exynos_core_save
[] = {
57 SAVE_ITEM(S5P_SROM_BW
),
58 SAVE_ITEM(S5P_SROM_BC0
),
59 SAVE_ITEM(S5P_SROM_BC1
),
60 SAVE_ITEM(S5P_SROM_BC2
),
61 SAVE_ITEM(S5P_SROM_BC3
),
64 struct exynos_pm_data
{
65 const struct exynos_wkup_irq
*wkup_irq
;
66 struct sleep_save
*extra_save
;
68 unsigned int wake_disable_mask
;
69 unsigned int *release_ret_regs
;
71 void (*pm_prepare
)(void);
72 void (*pm_resume_prepare
)(void);
73 void (*pm_resume
)(void);
74 int (*pm_suspend
)(void);
75 int (*cpu_suspend
)(unsigned long);
78 struct exynos_pm_data
*pm_data
;
80 static int exynos5420_cpu_state
;
81 static unsigned int exynos_pmu_spare3
;
87 static u32 exynos_irqwake_intmask
= 0xffffffff;
89 static const struct exynos_wkup_irq exynos3250_wkup_irq
[] = {
90 { 73, BIT(1) }, /* RTC alarm */
91 { 74, BIT(2) }, /* RTC tick */
95 static const struct exynos_wkup_irq exynos4_wkup_irq
[] = {
96 { 76, BIT(1) }, /* RTC alarm */
97 { 77, BIT(2) }, /* RTC tick */
101 static const struct exynos_wkup_irq exynos5250_wkup_irq
[] = {
102 { 75, BIT(1) }, /* RTC alarm */
103 { 76, BIT(2) }, /* RTC tick */
107 unsigned int exynos_release_ret_regs
[] = {
108 S5P_PAD_RET_MAUDIO_OPTION
,
109 S5P_PAD_RET_GPIO_OPTION
,
110 S5P_PAD_RET_UART_OPTION
,
111 S5P_PAD_RET_MMCA_OPTION
,
112 S5P_PAD_RET_MMCB_OPTION
,
113 S5P_PAD_RET_EBIA_OPTION
,
114 S5P_PAD_RET_EBIB_OPTION
,
118 unsigned int exynos3250_release_ret_regs
[] = {
119 S5P_PAD_RET_MAUDIO_OPTION
,
120 S5P_PAD_RET_GPIO_OPTION
,
121 S5P_PAD_RET_UART_OPTION
,
122 S5P_PAD_RET_MMCA_OPTION
,
123 S5P_PAD_RET_MMCB_OPTION
,
124 S5P_PAD_RET_EBIA_OPTION
,
125 S5P_PAD_RET_EBIB_OPTION
,
126 S5P_PAD_RET_MMC2_OPTION
,
127 S5P_PAD_RET_SPI_OPTION
,
131 unsigned int exynos5420_release_ret_regs
[] = {
132 EXYNOS_PAD_RET_DRAM_OPTION
,
133 EXYNOS_PAD_RET_MAUDIO_OPTION
,
134 EXYNOS_PAD_RET_JTAG_OPTION
,
135 EXYNOS5420_PAD_RET_GPIO_OPTION
,
136 EXYNOS5420_PAD_RET_UART_OPTION
,
137 EXYNOS5420_PAD_RET_MMCA_OPTION
,
138 EXYNOS5420_PAD_RET_MMCB_OPTION
,
139 EXYNOS5420_PAD_RET_MMCC_OPTION
,
140 EXYNOS5420_PAD_RET_HSI_OPTION
,
141 EXYNOS_PAD_RET_EBIA_OPTION
,
142 EXYNOS_PAD_RET_EBIB_OPTION
,
143 EXYNOS5420_PAD_RET_SPI_OPTION
,
144 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION
,
148 static int exynos_irq_set_wake(struct irq_data
*data
, unsigned int state
)
150 const struct exynos_wkup_irq
*wkup_irq
;
152 if (!pm_data
->wkup_irq
)
154 wkup_irq
= pm_data
->wkup_irq
;
156 while (wkup_irq
->mask
) {
157 if (wkup_irq
->hwirq
== data
->hwirq
) {
159 exynos_irqwake_intmask
|= wkup_irq
->mask
;
161 exynos_irqwake_intmask
&= ~wkup_irq
->mask
;
170 static int exynos_cpu_do_idle(void)
172 /* issue the standby signal into the pm unit. */
175 pr_info("Failed to suspend the system\n");
176 return 1; /* Aborting suspend */
178 static void exynos_flush_cache_all(void)
184 static int exynos_cpu_suspend(unsigned long arg
)
186 exynos_flush_cache_all();
187 return exynos_cpu_do_idle();
190 static int exynos3250_cpu_suspend(unsigned long arg
)
193 return exynos_cpu_do_idle();
196 static int exynos5420_cpu_suspend(unsigned long arg
)
198 /* MCPM works with HW CPU identifiers */
199 unsigned int mpidr
= read_cpuid_mpidr();
200 unsigned int cluster
= MPIDR_AFFINITY_LEVEL(mpidr
, 1);
201 unsigned int cpu
= MPIDR_AFFINITY_LEVEL(mpidr
, 0);
203 __raw_writel(0x0, sysram_base_addr
+ EXYNOS5420_CPU_STATE
);
205 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM
)) {
206 mcpm_set_entry_vector(cpu
, cluster
, exynos_cpu_resume
);
209 * Residency value passed to mcpm_cpu_suspend back-end
210 * has to be given clear semantics. Set to 0 as a
216 pr_info("Failed to suspend the system\n");
218 /* return value != 0 means failure */
222 static void exynos_pm_set_wakeup_mask(void)
224 /* Set wake-up mask registers */
225 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK
);
226 pmu_raw_writel(exynos_irqwake_intmask
& ~(1 << 31), S5P_WAKEUP_MASK
);
229 static void exynos_pm_enter_sleep_mode(void)
231 /* Set value of power down register for sleep mode */
232 exynos_sys_powerdown_conf(SYS_SLEEP
);
233 pmu_raw_writel(S5P_CHECK_SLEEP
, S5P_INFORM1
);
236 static void exynos_pm_prepare(void)
238 /* Set wake-up mask registers */
239 exynos_pm_set_wakeup_mask();
241 s3c_pm_do_save(exynos_core_save
, ARRAY_SIZE(exynos_core_save
));
243 if (pm_data
->extra_save
)
244 s3c_pm_do_save(pm_data
->extra_save
,
245 pm_data
->num_extra_save
);
247 exynos_pm_enter_sleep_mode();
249 /* ensure at least INFORM0 has the resume address */
250 pmu_raw_writel(virt_to_phys(exynos_cpu_resume
), S5P_INFORM0
);
253 static void exynos3250_pm_prepare(void)
257 /* Set wake-up mask registers */
258 exynos_pm_set_wakeup_mask();
260 tmp
= pmu_raw_readl(EXYNOS3_ARM_L2_OPTION
);
261 tmp
&= ~EXYNOS5_OPTION_USE_RETENTION
;
262 pmu_raw_writel(tmp
, EXYNOS3_ARM_L2_OPTION
);
264 exynos_pm_enter_sleep_mode();
266 /* ensure at least INFORM0 has the resume address */
267 pmu_raw_writel(virt_to_phys(exynos_cpu_resume
), S5P_INFORM0
);
270 static void exynos5420_pm_prepare(void)
274 /* Set wake-up mask registers */
275 exynos_pm_set_wakeup_mask();
277 s3c_pm_do_save(exynos_core_save
, ARRAY_SIZE(exynos_core_save
));
279 exynos_pmu_spare3
= pmu_raw_readl(S5P_PMU_SPARE3
);
281 * The cpu state needs to be saved and restored so that the
282 * secondary CPUs will enter low power start. Though the U-Boot
283 * is setting the cpu state with low power flag, the kernel
284 * needs to restore it back in case, the primary cpu fails to
285 * suspend for any reason.
287 exynos5420_cpu_state
= __raw_readl(sysram_base_addr
+
288 EXYNOS5420_CPU_STATE
);
290 exynos_pm_enter_sleep_mode();
292 /* ensure at least INFORM0 has the resume address */
293 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM
))
294 pmu_raw_writel(virt_to_phys(mcpm_entry_point
), S5P_INFORM0
);
296 tmp
= pmu_raw_readl(EXYNOS5_ARM_L2_OPTION
);
297 tmp
&= ~EXYNOS5_USE_RETENTION
;
298 pmu_raw_writel(tmp
, EXYNOS5_ARM_L2_OPTION
);
300 tmp
= pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1
);
301 tmp
|= EXYNOS5420_UFS
;
302 pmu_raw_writel(tmp
, EXYNOS5420_SFR_AXI_CGDIS1
);
304 tmp
= pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION
);
305 tmp
&= ~EXYNOS5420_L2RSTDISABLE_VALUE
;
306 pmu_raw_writel(tmp
, EXYNOS5420_ARM_COMMON_OPTION
);
308 tmp
= pmu_raw_readl(EXYNOS5420_FSYS2_OPTION
);
309 tmp
|= EXYNOS5420_EMULATION
;
310 pmu_raw_writel(tmp
, EXYNOS5420_FSYS2_OPTION
);
312 tmp
= pmu_raw_readl(EXYNOS5420_PSGEN_OPTION
);
313 tmp
|= EXYNOS5420_EMULATION
;
314 pmu_raw_writel(tmp
, EXYNOS5420_PSGEN_OPTION
);
318 static int exynos_pm_suspend(void)
320 exynos_pm_central_suspend();
322 /* Setting SEQ_OPTION register */
323 pmu_raw_writel(S5P_USE_STANDBY_WFI0
| S5P_USE_STANDBY_WFE0
,
324 S5P_CENTRAL_SEQ_OPTION
);
326 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
)
327 exynos_cpu_save_register();
332 static int exynos5420_pm_suspend(void)
336 exynos_pm_central_suspend();
338 /* Setting SEQ_OPTION register */
340 this_cluster
= MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
342 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0
,
343 S5P_CENTRAL_SEQ_OPTION
);
345 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0
,
346 S5P_CENTRAL_SEQ_OPTION
);
350 static void exynos_pm_release_retention(void)
354 for (i
= 0; (pm_data
->release_ret_regs
[i
] != REG_TABLE_END
); i
++)
355 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR
,
356 pm_data
->release_ret_regs
[i
]);
359 static void exynos_pm_resume(void)
361 u32 cpuid
= read_cpuid_part();
363 if (exynos_pm_central_resume())
366 /* For release retention */
367 exynos_pm_release_retention();
369 if (pm_data
->extra_save
)
370 s3c_pm_do_restore_core(pm_data
->extra_save
,
371 pm_data
->num_extra_save
);
373 s3c_pm_do_restore_core(exynos_core_save
, ARRAY_SIZE(exynos_core_save
));
375 if (cpuid
== ARM_CPU_PART_CORTEX_A9
)
376 scu_enable(S5P_VA_SCU
);
378 if (call_firmware_op(resume
) == -ENOSYS
379 && cpuid
== ARM_CPU_PART_CORTEX_A9
)
380 exynos_cpu_restore_register();
384 /* Clear SLEEP mode set in INFORM1 */
385 pmu_raw_writel(0x0, S5P_INFORM1
);
388 static void exynos3250_pm_resume(void)
390 u32 cpuid
= read_cpuid_part();
392 if (exynos_pm_central_resume())
395 /* For release retention */
396 exynos_pm_release_retention();
398 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL
, S5P_CENTRAL_SEQ_OPTION
);
400 if (call_firmware_op(resume
) == -ENOSYS
401 && cpuid
== ARM_CPU_PART_CORTEX_A9
)
402 exynos_cpu_restore_register();
406 /* Clear SLEEP mode set in INFORM1 */
407 pmu_raw_writel(0x0, S5P_INFORM1
);
410 static void exynos5420_prepare_pm_resume(void)
412 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM
))
413 WARN_ON(mcpm_cpu_powered_up());
416 static void exynos5420_pm_resume(void)
420 /* Restore the CPU0 low power state register */
421 tmp
= pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG
);
422 pmu_raw_writel(tmp
| S5P_CORE_LOCAL_PWR_EN
,
423 EXYNOS5_ARM_CORE0_SYS_PWR_REG
);
425 /* Restore the sysram cpu state register */
426 __raw_writel(exynos5420_cpu_state
,
427 sysram_base_addr
+ EXYNOS5420_CPU_STATE
);
429 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL
,
430 S5P_CENTRAL_SEQ_OPTION
);
432 if (exynos_pm_central_resume())
435 /* For release retention */
436 exynos_pm_release_retention();
438 pmu_raw_writel(exynos_pmu_spare3
, S5P_PMU_SPARE3
);
440 s3c_pm_do_restore_core(exynos_core_save
, ARRAY_SIZE(exynos_core_save
));
444 tmp
= pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1
);
445 tmp
&= ~EXYNOS5420_UFS
;
446 pmu_raw_writel(tmp
, EXYNOS5420_SFR_AXI_CGDIS1
);
448 tmp
= pmu_raw_readl(EXYNOS5420_FSYS2_OPTION
);
449 tmp
&= ~EXYNOS5420_EMULATION
;
450 pmu_raw_writel(tmp
, EXYNOS5420_FSYS2_OPTION
);
452 tmp
= pmu_raw_readl(EXYNOS5420_PSGEN_OPTION
);
453 tmp
&= ~EXYNOS5420_EMULATION
;
454 pmu_raw_writel(tmp
, EXYNOS5420_PSGEN_OPTION
);
456 /* Clear SLEEP mode set in INFORM1 */
457 pmu_raw_writel(0x0, S5P_INFORM1
);
464 static int exynos_suspend_enter(suspend_state_t state
)
470 S3C_PMDBG("%s: suspending the system...\n", __func__
);
472 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__
,
473 exynos_irqwake_intmask
, exynos_get_eint_wake_mask());
475 if (exynos_irqwake_intmask
== -1U
476 && exynos_get_eint_wake_mask() == -1U) {
477 pr_err("%s: No wake-up sources!\n", __func__
);
478 pr_err("%s: Aborting sleep\n", __func__
);
483 if (pm_data
->pm_prepare
)
484 pm_data
->pm_prepare();
486 s3c_pm_check_store();
488 ret
= call_firmware_op(suspend
);
490 ret
= cpu_suspend(0, pm_data
->cpu_suspend
);
494 if (pm_data
->pm_resume_prepare
)
495 pm_data
->pm_resume_prepare();
496 s3c_pm_restore_uarts();
498 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__
,
499 pmu_raw_readl(S5P_WAKEUP_STAT
));
501 s3c_pm_check_restore();
503 S3C_PMDBG("%s: resuming the system...\n", __func__
);
508 static int exynos_suspend_prepare(void)
513 * REVISIT: It would be better if struct platform_suspend_ops
514 * .prepare handler get the suspend_state_t as a parameter to
515 * avoid hard-coding the suspend to mem state. It's safe to do
516 * it now only because the suspend_valid_only_mem function is
517 * used as the .valid callback used to check if a given state
518 * is supported by the platform anyways.
520 ret
= regulator_suspend_prepare(PM_SUSPEND_MEM
);
522 pr_err("Failed to prepare regulators for suspend (%d)\n", ret
);
526 s3c_pm_check_prepare();
531 static void exynos_suspend_finish(void)
535 s3c_pm_check_cleanup();
537 ret
= regulator_suspend_finish();
539 pr_warn("Failed to resume regulators from suspend (%d)\n", ret
);
542 static const struct platform_suspend_ops exynos_suspend_ops
= {
543 .enter
= exynos_suspend_enter
,
544 .prepare
= exynos_suspend_prepare
,
545 .finish
= exynos_suspend_finish
,
546 .valid
= suspend_valid_only_mem
,
549 static const struct exynos_pm_data exynos3250_pm_data
= {
550 .wkup_irq
= exynos3250_wkup_irq
,
551 .wake_disable_mask
= ((0xFF << 8) | (0x1F << 1)),
552 .release_ret_regs
= exynos3250_release_ret_regs
,
553 .pm_suspend
= exynos_pm_suspend
,
554 .pm_resume
= exynos3250_pm_resume
,
555 .pm_prepare
= exynos3250_pm_prepare
,
556 .cpu_suspend
= exynos3250_cpu_suspend
,
559 static const struct exynos_pm_data exynos4_pm_data
= {
560 .wkup_irq
= exynos4_wkup_irq
,
561 .wake_disable_mask
= ((0xFF << 8) | (0x1F << 1)),
562 .release_ret_regs
= exynos_release_ret_regs
,
563 .pm_suspend
= exynos_pm_suspend
,
564 .pm_resume
= exynos_pm_resume
,
565 .pm_prepare
= exynos_pm_prepare
,
566 .cpu_suspend
= exynos_cpu_suspend
,
569 static const struct exynos_pm_data exynos5250_pm_data
= {
570 .wkup_irq
= exynos5250_wkup_irq
,
571 .wake_disable_mask
= ((0xFF << 8) | (0x1F << 1)),
572 .release_ret_regs
= exynos_release_ret_regs
,
573 .pm_suspend
= exynos_pm_suspend
,
574 .pm_resume
= exynos_pm_resume
,
575 .pm_prepare
= exynos_pm_prepare
,
576 .cpu_suspend
= exynos_cpu_suspend
,
579 static struct exynos_pm_data exynos5420_pm_data
= {
580 .wkup_irq
= exynos5250_wkup_irq
,
581 .wake_disable_mask
= (0x7F << 7) | (0x1F << 1),
582 .release_ret_regs
= exynos5420_release_ret_regs
,
583 .pm_resume_prepare
= exynos5420_prepare_pm_resume
,
584 .pm_resume
= exynos5420_pm_resume
,
585 .pm_suspend
= exynos5420_pm_suspend
,
586 .pm_prepare
= exynos5420_pm_prepare
,
587 .cpu_suspend
= exynos5420_cpu_suspend
,
590 static const struct of_device_id exynos_pmu_of_device_ids
[] __initconst
= {
592 .compatible
= "samsung,exynos3250-pmu",
593 .data
= &exynos3250_pm_data
,
595 .compatible
= "samsung,exynos4210-pmu",
596 .data
= &exynos4_pm_data
,
598 .compatible
= "samsung,exynos4212-pmu",
599 .data
= &exynos4_pm_data
,
601 .compatible
= "samsung,exynos4412-pmu",
602 .data
= &exynos4_pm_data
,
604 .compatible
= "samsung,exynos5250-pmu",
605 .data
= &exynos5250_pm_data
,
607 .compatible
= "samsung,exynos5420-pmu",
608 .data
= &exynos5420_pm_data
,
613 static struct syscore_ops exynos_pm_syscore_ops
;
615 void __init
exynos_pm_init(void)
617 const struct of_device_id
*match
;
620 of_find_matching_node_and_match(NULL
, exynos_pmu_of_device_ids
, &match
);
622 pr_err("Failed to find PMU node\n");
625 pm_data
= (struct exynos_pm_data
*) match
->data
;
627 /* Platform-specific GIC callback */
628 gic_arch_extn
.irq_set_wake
= exynos_irq_set_wake
;
630 /* All wakeup disable */
631 tmp
= pmu_raw_readl(S5P_WAKEUP_MASK
);
632 tmp
|= pm_data
->wake_disable_mask
;
633 pmu_raw_writel(tmp
, S5P_WAKEUP_MASK
);
635 exynos_pm_syscore_ops
.suspend
= pm_data
->pm_suspend
;
636 exynos_pm_syscore_ops
.resume
= pm_data
->pm_resume
;
638 register_syscore_ops(&exynos_pm_syscore_ops
);
639 suspend_set_ops(&exynos_suspend_ops
);