arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19 #include <asm/hardware/gic.h>
  20
  21 #include <plat/cpu.h>
  22 #include <plat/clock.h>
  23 #include <plat/devs.h>
  24 #include <plat/exynos4.h>
  25 #include <plat/adc-core.h>
  26 #include <plat/sdhci.h>
  27 #include <plat/fb-core.h>
  28 #include <plat/fimc-core.h>
  29 #include <plat/iic-core.h>
  30 #include <plat/reset.h>
  31 #include <plat/tv-core.h>
  32
  33 #include <mach/regs-irq.h>
  34 #include <mach/regs-pmu.h>
  35
  36 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  37                          unsigned int irq_start);
  38 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  39
  40 /* Initial IO mappings */
  41 static struct map_desc exynos4_iodesc[] __initdata = {
  42         {
  43                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  44                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  45                 .length         = SZ_4K,
  46                 .type           = MT_DEVICE,
  47         }, {
  48                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  49                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
  50                 .length         = SZ_4K,
  51                 .type           = MT_DEVICE,
  52         }, {
  53                 .virtual        = (unsigned long)S5P_VA_CMU,
  54                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  55                 .length         = SZ_128K,
  56                 .type           = MT_DEVICE,
  57         }, {
  58                 .virtual        = (unsigned long)S5P_VA_PMU,
  59                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  60                 .length         = SZ_64K,
  61                 .type           = MT_DEVICE,
  62         }, {
  63                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  64                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  65                 .length         = SZ_4K,
  66                 .type           = MT_DEVICE,
  67         }, {
  68                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  69                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  70                 .length         = SZ_8K,
  71                 .type           = MT_DEVICE,
  72         }, {
  73                 .virtual        = (unsigned long)S5P_VA_L2CC,
  74                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  75                 .length         = SZ_4K,
  76                 .type           = MT_DEVICE,
  77         }, {
  78                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  79                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  80                 .length         = SZ_4K,
  81                 .type           = MT_DEVICE,
  82         }, {
  83                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  84                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  85                 .length         = SZ_4K,
  86                 .type           = MT_DEVICE,
  87         }, {
  88                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  89                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  90                 .length         = SZ_256,
  91                 .type           = MT_DEVICE,
  92         }, {
  93                 .virtual        = (unsigned long)S5P_VA_DMC0,
  94                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE,
  97         }, {
  98                 .virtual        = (unsigned long)S3C_VA_UART,
  99                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 100                 .length         = SZ_512K,
 101                 .type           = MT_DEVICE,
 102         }, {
 103                 .virtual        = (unsigned long)S5P_VA_SROMC,
 104                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE,
 107         }, {
 108                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 109                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE,
 112         }, {
 113                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 114                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 115                 .length         = SZ_64K,
 116                 .type           = MT_DEVICE,
 117         }, {
 118                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 119                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 120                 .length         = SZ_64K,
 121                 .type           = MT_DEVICE,
 122         },
 123 };
 124
 125 static void exynos4_idle(void)
 126 {
 127         if (!need_resched())
 128                 cpu_do_idle();
 129
 130         local_irq_enable();
 131 }
 132
 133 static void exynos4_sw_reset(void)
 134 {
 135         __raw_writel(0x1, S5P_SWRESET);
 136 }
 137
 138 /*
 139  * exynos4_map_io
 140  *
 141  * register the standard cpu IO areas
 142  */
 143 void __init exynos4_map_io(void)
 144 {
 145         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 146
 147         /* initialize device information early */
 148         exynos4_default_sdhci0();
 149         exynos4_default_sdhci1();
 150         exynos4_default_sdhci2();
 151         exynos4_default_sdhci3();
 152
 153         s3c_adc_setname("samsung-adc-v3");
 154
 155         s3c_fimc_setname(0, "exynos4-fimc");
 156         s3c_fimc_setname(1, "exynos4-fimc");
 157         s3c_fimc_setname(2, "exynos4-fimc");
 158         s3c_fimc_setname(3, "exynos4-fimc");
 159
 160         /* The I2C bus controllers are directly compatible with s3c2440 */
 161         s3c_i2c0_setname("s3c2440-i2c");
 162         s3c_i2c1_setname("s3c2440-i2c");
 163         s3c_i2c2_setname("s3c2440-i2c");
 164
 165         s5p_fb_setname(0, "exynos4-fb");
 166         s5p_hdmi_setname("exynos4-hdmi");
 167 }
 168
 169 void __init exynos4_init_clocks(int xtal)
 170 {
 171         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 172
 173         s3c24xx_register_baseclocks(xtal);
 174         s5p_register_clocks(xtal);
 175         exynos4_register_clocks();
 176         exynos4_setup_clocks();
 177 }
 178
 179 static void exynos4_gic_irq_eoi(struct irq_data *d)
 180 {
 181         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 182
 183         gic_data->cpu_base = S5P_VA_GIC_CPU +
 184                             (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
 185 }
 186
 187 void __init exynos4_init_irq(void)
 188 {
 189         int irq;
 190
 191         gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 192         gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
 193
 194         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 195
 196                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 197                                 COMBINER_IRQ(irq, 0));
 198                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 199         }
 200
 201         /* The parameters of s5p_init_irq() are for VIC init.
 202          * Theses parameters should be NULL and 0 because EXYNOS4
 203          * uses GIC instead of VIC.
 204          */
 205         s5p_init_irq(NULL, 0);
 206 }
 207
 208 struct sysdev_class exynos4_sysclass = {
 209         .name   = "exynos4-core",
 210 };
 211
 212 static struct sys_device exynos4_sysdev = {
 213         .cls    = &exynos4_sysclass,
 214 };
 215
 216 static int __init exynos4_core_init(void)
 217 {
 218         return sysdev_class_register(&exynos4_sysclass);
 219 }
 220
 221 core_initcall(exynos4_core_init);
 222
 223 #ifdef CONFIG_CACHE_L2X0
 224 static int __init exynos4_l2x0_cache_init(void)
 225 {
 226         /* TAG, Data Latency Control: 2cycle */
 227         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 228         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 229
 230         /* L2X0 Prefetch Control */
 231         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 232
 233         /* L2X0 Power Control */
 234         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 235                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 236
 237         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 238
 239         return 0;
 240 }
 241
 242 early_initcall(exynos4_l2x0_cache_init);
 243 #endif
 244
 245 int __init exynos4_init(void)
 246 {
 247         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 248
 249         /* set idle function */
 250         pm_idle = exynos4_idle;
 251
 252         /* set sw_reset function */
 253         s5p_reset_hook = exynos4_sw_reset;
 254
 255         return sysdev_register(&exynos4_sysdev);
 256 }