arch/arm/mach-exynos4/include/mach/map.h

   1 /* linux/arch/arm/mach-exynos4/include/mach/map.h
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * EXYNOS4 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_MAP_H
  14 #define __ASM_ARCH_MAP_H __FILE__
  15
  16 #include <plat/map-base.h>
  17
  18 /*
  19  * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
  20  * So need to define it, and here is to avoid redefinition warning.
  21  */
  22 #define S3C_UART_OFFSET                 (0x10000)
  23
  24 #include <plat/map-s5p.h>
  25
  26 #define EXYNOS4_PA_SYSRAM0              0x02025000
  27 #define EXYNOS4_PA_SYSRAM1              0x02020000
  28
  29 #define EXYNOS4_PA_FIMC0                0x11800000
  30 #define EXYNOS4_PA_FIMC1                0x11810000
  31 #define EXYNOS4_PA_FIMC2                0x11820000
  32 #define EXYNOS4_PA_FIMC3                0x11830000
  33
  34 #define EXYNOS4_PA_I2S0                 0x03830000
  35 #define EXYNOS4_PA_I2S1                 0xE3100000
  36 #define EXYNOS4_PA_I2S2                 0xE2A00000
  37
  38 #define EXYNOS4_PA_PCM0                 0x03840000
  39 #define EXYNOS4_PA_PCM1                 0x13980000
  40 #define EXYNOS4_PA_PCM2                 0x13990000
  41
  42 #define EXYNOS4_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
  43
  44 #define EXYNOS4_PA_ONENAND              0x0C000000
  45 #define EXYNOS4_PA_ONENAND_DMA          0x0C600000
  46
  47 #define EXYNOS4_PA_CHIPID               0x10000000
  48
  49 #define EXYNOS4_PA_SYSCON               0x10010000
  50 #define EXYNOS4_PA_PMU                  0x10020000
  51 #define EXYNOS4_PA_CMU                  0x10030000
  52
  53 #define EXYNOS4_PA_SYSTIMER             0x10050000
  54 #define EXYNOS4_PA_WATCHDOG             0x10060000
  55 #define EXYNOS4_PA_RTC                  0x10070000
  56
  57 #define EXYNOS4_PA_KEYPAD               0x100A0000
  58
  59 #define EXYNOS4_PA_DMC0                 0x10400000
  60
  61 #define EXYNOS4_PA_COMBINER             0x10440000
  62
  63 #define EXYNOS4_PA_GIC_CPU              0x10480000
  64 #define EXYNOS4_PA_GIC_DIST             0x10490000
  65 #define EXYNOS4_GIC_BANK_OFFSET         0x8000
  66
  67 #define EXYNOS4_PA_COREPERI             0x10500000
  68 #define EXYNOS4_PA_TWD                  0x10500600
  69 #define EXYNOS4_PA_L2CC                 0x10502000
  70
  71 #define EXYNOS4_PA_MDMA                 0x10810000
  72 #define EXYNOS4_PA_PDMA0                0x12680000
  73 #define EXYNOS4_PA_PDMA1                0x12690000
  74
  75 #define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
  76 #define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
  77 #define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
  78 #define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
  79 #define EXYNOS4_PA_SYSMMU_FIMC2         0x11A40000
  80 #define EXYNOS4_PA_SYSMMU_FIMC3         0x11A50000
  81 #define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
  82 #define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
  83 #define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
  84 #define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
  85 #define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
  86 #define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
  87 #define EXYNOS4_PA_SYSMMU_MDMA2         0x12A40000
  88 #define EXYNOS4_PA_SYSMMU_TV            0x12E20000
  89 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
  90 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
  91
  92 #define EXYNOS4_PA_GPIO1                0x11400000
  93 #define EXYNOS4_PA_GPIO2                0x11000000
  94 #define EXYNOS4_PA_GPIO3                0x03860000
  95
  96 #define EXYNOS4_PA_MIPI_CSIS0           0x11880000
  97 #define EXYNOS4_PA_MIPI_CSIS1           0x11890000
  98
  99 #define EXYNOS4_PA_FIMD0                0x11C00000
 100
 101 #define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 102 #define EXYNOS4_PA_DWMCI                0x12550000
 103
 104 #define EXYNOS4_PA_SATA                 0x12560000
 105 #define EXYNOS4_PA_SATAPHY              0x125D0000
 106 #define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
 107
 108 #define EXYNOS4_PA_SROMC                0x12570000
 109
 110 #define EXYNOS4_PA_EHCI                 0x12580000
 111 #define EXYNOS4_PA_HSPHY                0x125B0000
 112 #define EXYNOS4_PA_MFC                  0x13400000
 113
 114 #define EXYNOS4_PA_UART                 0x13800000
 115
 116 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
 117
 118 #define EXYNOS4_PA_ADC                  0x13910000
 119 #define EXYNOS4_PA_ADC1                 0x13911000
 120
 121 #define EXYNOS4_PA_AC97                 0x139A0000
 122
 123 #define EXYNOS4_PA_SPDIF                0x139B0000
 124
 125 #define EXYNOS4_PA_TIMER                0x139D0000
 126
 127 #define EXYNOS4_PA_SDRAM                0x40000000
 128
 129 /* Compatibiltiy Defines */
 130
 131 #define S3C_PA_HSMMC0                   EXYNOS4_PA_HSMMC(0)
 132 #define S3C_PA_HSMMC1                   EXYNOS4_PA_HSMMC(1)
 133 #define S3C_PA_HSMMC2                   EXYNOS4_PA_HSMMC(2)
 134 #define S3C_PA_HSMMC3                   EXYNOS4_PA_HSMMC(3)
 135 #define S3C_PA_IIC                      EXYNOS4_PA_IIC(0)
 136 #define S3C_PA_IIC1                     EXYNOS4_PA_IIC(1)
 137 #define S3C_PA_IIC2                     EXYNOS4_PA_IIC(2)
 138 #define S3C_PA_IIC3                     EXYNOS4_PA_IIC(3)
 139 #define S3C_PA_IIC4                     EXYNOS4_PA_IIC(4)
 140 #define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
 141 #define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
 142 #define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
 143 #define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
 144 #define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
 145 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 146 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
 147
 148 #define S5P_PA_CHIPID                   EXYNOS4_PA_CHIPID
 149 #define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
 150 #define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
 151 #define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
 152 #define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
 153 #define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
 154 #define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
 155 #define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
 156 #define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
 157 #define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
 158 #define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
 159 #define S5P_PA_SROMC                    EXYNOS4_PA_SROMC
 160 #define S5P_PA_MFC                      EXYNOS4_PA_MFC
 161 #define S5P_PA_SYSCON                   EXYNOS4_PA_SYSCON
 162 #define S5P_PA_TIMER                    EXYNOS4_PA_TIMER
 163 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 164
 165 #define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
 166
 167 /* UART */
 168
 169 #define S3C_PA_UART                     EXYNOS4_PA_UART
 170
 171 #define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
 172 #define S5P_PA_UART0                    S5P_PA_UART(0)
 173 #define S5P_PA_UART1                    S5P_PA_UART(1)
 174 #define S5P_PA_UART2                    S5P_PA_UART(2)
 175 #define S5P_PA_UART3                    S5P_PA_UART(3)
 176 #define S5P_PA_UART4                    S5P_PA_UART(4)
 177
 178 #define S5P_SZ_UART                     SZ_256
 179
 180 #endif /* __ASM_ARCH_MAP_H */