arch/arm/mach-exynos4/pmu.c

   1 /* linux/arch/arm/mach-exynos4/pmu.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * EXYNOS4210 - CPU PMU(Power Management Unit) support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15
  16 #include <mach/regs-clock.h>
  17 #include <mach/pmu.h>
  18
  19 static struct exynos4_pmu_conf *exynos4_pmu_config;
  20
  21 static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
  22         /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
  23         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
  24         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
  25         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
  26         { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
  27         { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
  28         { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
  29         { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
  30         { S5P_L2_0_LOWPWR,                      { 0x2, 0x2, 0x3 } },
  31         { S5P_L2_1_LOWPWR,                      { 0x2, 0x2, 0x3 } },
  32         { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
  33         { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
  34         { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
  35         { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
  36         { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
  37         { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
  38         { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
  39         { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x1, 0x0 } },
  40         { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x1, 0x0 } },
  41         { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x1, 0x0 } },
  42         { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x1, 0x0 } },
  43         { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x1, 0x0 } },
  44         { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x1, 0x0 } },
  45         { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x1, 0x0 } },
  46         { S5P_CMU_CLKSTOP_LCD1_LOWPWR,          { 0x1, 0x1, 0x0 } },
  47         { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x1, 0x0 } },
  48         { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x1, 0x0 } },
  49         { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x1, 0x0 } },
  50         { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x1, 0x0 } },
  51         { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x1, 0x0 } },
  52         { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x1, 0x0 } },
  53         { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x1, 0x0 } },
  54         { S5P_CMU_RESET_LCD1_LOWPWR,            { 0x1, 0x1, 0x0 } },
  55         { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
  56         { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x1, 0x0 } },
  57         { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
  58         { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
  59         { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
  60         { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
  61         { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
  62         { S5P_MODIMIF_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
  63         { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
  64         { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
  65         { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
  66         { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
  67         { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
  68         { S5P_PCIE_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
  69         { S5P_SATA_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
  70         { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
  71         { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
  72         { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
  73         { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
  74         { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
  75         { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
  76         { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
  77         { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
  78         { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
  79         { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
  80         { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
  81         { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
  82         { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
  83         { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
  84         { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
  85         { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
  86         { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
  87         { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
  88         { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
  89         { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
  90         { S5P_LCD1_LOWPWR,                      { 0x7, 0x0, 0x0 } },
  91         { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
  92         { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
  93         { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
  94         { PMU_TABLE_END,},
  95 };
  96
  97 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
  98 {
  99         unsigned int i;
 100
 101         for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
 102                 __raw_writel(exynos4_pmu_config[i].val[mode],
 103                                 exynos4_pmu_config[i].reg);
 104 }
 105
 106 static int __init exynos4_pmu_init(void)
 107 {
 108         exynos4_pmu_config = exynos4210_pmu_config;
 109
 110         pr_info("EXYNOS4210 PMU Initialize\n");
 111
 112         return 0;
 113 }
 114 arch_initcall(exynos4_pmu_init);