arch/arm/mach-footbridge/dc21285-timer.c

   1 /*
   2  *  linux/arch/arm/mach-footbridge/dc21285-timer.c
   3  *
   4  *  Copyright (C) 1998 Russell King.
   5  *  Copyright (C) 1998 Phil Blundell
   6  */
   7 #include <linux/clockchips.h>
   8 #include <linux/clocksource.h>
   9 #include <linux/init.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/irq.h>
  12 #include <linux/sched_clock.h>
  13
  14 #include <asm/irq.h>
  15
  16 #include <asm/hardware/dec21285.h>
  17 #include <asm/mach/time.h>
  18 #include <asm/system_info.h>
  19
  20 #include "common.h"
  21
  22 static cycle_t cksrc_dc21285_read(struct clocksource *cs)
  23 {
  24         return cs->mask - *CSR_TIMER2_VALUE;
  25 }
  26
  27 static int cksrc_dc21285_enable(struct clocksource *cs)
  28 {
  29         *CSR_TIMER2_LOAD = cs->mask;
  30         *CSR_TIMER2_CLR = 0;
  31         *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
  32         return 0;
  33 }
  34
  35 static void cksrc_dc21285_disable(struct clocksource *cs)
  36 {
  37         *CSR_TIMER2_CNTL = 0;
  38 }
  39
  40 static struct clocksource cksrc_dc21285 = {
  41         .name           = "dc21285_timer2",
  42         .rating         = 200,
  43         .read           = cksrc_dc21285_read,
  44         .enable         = cksrc_dc21285_enable,
  45         .disable        = cksrc_dc21285_disable,
  46         .mask           = CLOCKSOURCE_MASK(24),
  47         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  48 };
  49
  50 static int ckevt_dc21285_set_next_event(unsigned long delta,
  51         struct clock_event_device *c)
  52 {
  53         *CSR_TIMER1_CLR = 0;
  54         *CSR_TIMER1_LOAD = delta;
  55         *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
  56
  57         return 0;
  58 }
  59
  60 static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
  61         struct clock_event_device *c)
  62 {
  63         switch (mode) {
  64         case CLOCK_EVT_MODE_RESUME:
  65         case CLOCK_EVT_MODE_PERIODIC:
  66                 *CSR_TIMER1_CLR = 0;
  67                 *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
  68                 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
  69                                    TIMER_CNTL_DIV16;
  70                 break;
  71
  72         case CLOCK_EVT_MODE_ONESHOT:
  73         case CLOCK_EVT_MODE_UNUSED:
  74         case CLOCK_EVT_MODE_SHUTDOWN:
  75                 *CSR_TIMER1_CNTL = 0;
  76                 break;
  77         }
  78 }
  79
  80 static struct clock_event_device ckevt_dc21285 = {
  81         .name           = "dc21285_timer1",
  82         .features       = CLOCK_EVT_FEAT_PERIODIC |
  83                           CLOCK_EVT_FEAT_ONESHOT,
  84         .rating         = 200,
  85         .irq            = IRQ_TIMER1,
  86         .set_next_event = ckevt_dc21285_set_next_event,
  87         .set_mode       = ckevt_dc21285_set_mode,
  88 };
  89
  90 static irqreturn_t timer1_interrupt(int irq, void *dev_id)
  91 {
  92         struct clock_event_device *ce = dev_id;
  93
  94         *CSR_TIMER1_CLR = 0;
  95
  96         /* Stop the timer if in one-shot mode */
  97         if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
  98                 *CSR_TIMER1_CNTL = 0;
  99
 100         ce->event_handler(ce);
 101
 102         return IRQ_HANDLED;
 103 }
 104
 105 static struct irqaction footbridge_timer_irq = {
 106         .name           = "dc21285_timer1",
 107         .handler        = timer1_interrupt,
 108         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 109         .dev_id         = &ckevt_dc21285,
 110 };
 111
 112 /*
 113  * Set up timer interrupt.
 114  */
 115 void __init footbridge_timer_init(void)
 116 {
 117         struct clock_event_device *ce = &ckevt_dc21285;
 118         unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
 119
 120         clocksource_register_hz(&cksrc_dc21285, rate);
 121
 122         setup_irq(ce->irq, &footbridge_timer_irq);
 123
 124         ce->cpumask = cpumask_of(smp_processor_id());
 125         clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
 126 }
 127
 128 static u32 notrace footbridge_read_sched_clock(void)
 129 {
 130         return ~*CSR_TIMER3_VALUE;
 131 }
 132
 133 void __init footbridge_sched_clock(void)
 134 {
 135         unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
 136
 137         *CSR_TIMER3_LOAD = 0;
 138         *CSR_TIMER3_CLR = 0;
 139         *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
 140
 141         setup_sched_clock(footbridge_read_sched_clock, 24, rate);
 142 }