arch/arm/mach-imx/clk-imx51-imx53.c

   1 /*
   2  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9 #include <linux/mm.h>
  10 #include <linux/delay.h>
  11 #include <linux/clk.h>
  12 #include <linux/io.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/of.h>
  15 #include <linux/err.h>
  16
  17 #include "crm-regs-imx5.h"
  18 #include "clk.h"
  19 #include "common.h"
  20 #include "hardware.h"
  21
  22 /* Low-power Audio Playback Mode clock */
  23 static const char *lp_apm_sel[] = { "osc", };
  24
  25 /* This is used multiple times */
  26 static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
  27 static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
  28 static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
  29 static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
  30 static const char *per_root_sel[] = { "per_podf", "ipg", };
  31 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
  32 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
  33 static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
  34 static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
  35 static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
  36 static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
  37 static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
  38 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
  39 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
  40 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
  41 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
  42 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
  43 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
  44 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
  45 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
  46 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
  47 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
  48 static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
  49 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
  50 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
  51 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
  52
  53 enum imx5_clks {
  54         dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
  55         uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
  56         emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
  57         usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
  58         tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
  59         uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
  60         gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
  61         gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
  62         esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
  63         ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
  64         ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
  65         ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
  66         vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
  67         uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
  68         esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
  69         mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
  70         ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
  71         ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
  72         periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
  73         tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
  74         esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
  75         usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
  76         pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
  77         ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
  78         usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
  79         ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
  80         ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
  81         ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
  82         ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
  83         ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
  84         epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
  85         can_sel, can1_serial_gate, can1_ipg_gate,
  86         owire_gate,
  87         clk_max
  88 };
  89
  90 static struct clk *clk[clk_max];
  91 static struct clk_onecell_data clk_data;
  92
  93 static void __init mx5_clocks_common_init(unsigned long rate_ckil,
  94                 unsigned long rate_osc, unsigned long rate_ckih1,
  95                 unsigned long rate_ckih2)
  96 {
  97         int i;
  98
  99         clk[dummy] = imx_clk_fixed("dummy", 0);
 100         clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
 101         clk[osc] = imx_clk_fixed("osc", rate_osc);
 102         clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
 103         clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
 104
 105         clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
 106                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
 107         clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
 108                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
 109         clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
 110                                 main_bus_sel, ARRAY_SIZE(main_bus_sel));
 111         clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
 112                                 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
 113         clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
 114         clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
 115         clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
 116         clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
 117                                 per_root_sel, ARRAY_SIZE(per_root_sel));
 118         clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
 119         clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
 120         clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
 121         clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
 122         clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
 123         clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
 124         clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
 125         clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
 126         clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
 127         clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
 128         clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
 129         clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
 130                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 131         clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
 132         clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
 133
 134         clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
 135                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 136         clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
 137                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 138         clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
 139         clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
 140         clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
 141         clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
 142         clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
 143         clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 144
 145         clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
 146                                 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
 147         clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
 148         clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
 149         clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
 150                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 151         clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
 152         clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
 153         clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
 154                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 155         clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
 156         clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
 157         clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
 158         clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
 159         clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
 160                                 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
 161         clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
 162         clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
 163         clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
 164         clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
 165         clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
 166         clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
 167         clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
 168         clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
 169         clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
 170         clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
 171         clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
 172         clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
 173         clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
 174         clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
 175         clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
 176         clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
 177         clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
 178         clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
 179         clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
 180         clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
 181         clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
 182         clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
 183         clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
 184         clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
 185         clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
 186         clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
 187         clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
 188         clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
 189         clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
 190         clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
 191         clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
 192         clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
 193         clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
 194         clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
 195         clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
 196         clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
 197         clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
 198         clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
 199         clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
 200         clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
 201         clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
 202         clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
 203         clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
 204         clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
 205         clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
 206         clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
 207         clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
 208         clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
 209         clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
 210         clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
 211
 212         clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
 213         clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 214         clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 215         clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
 216         clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 217         clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 218         clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
 219         clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
 220         clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
 221         clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
 222         clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
 223         clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
 224         clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
 225         clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
 226         clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
 227         clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
 228         clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
 229         clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
 230         clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
 231         clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
 232         clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
 233         clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
 234         clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
 235         clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
 236         clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
 237         clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
 238
 239         for (i = 0; i < ARRAY_SIZE(clk); i++)
 240                 if (IS_ERR(clk[i]))
 241                         pr_err("i.MX5 clk %d: register failed with %ld\n",
 242                                 i, PTR_ERR(clk[i]));
 243
 244         clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
 245         clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
 246         clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
 247         clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
 248         clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
 249         clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
 250         clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
 251         clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
 252         clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
 253         clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
 254         clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
 255         clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
 256         clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
 257         clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
 258         clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
 259         clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
 260         clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
 261         clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
 262         clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
 263         clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
 264         clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
 265         clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
 266         clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
 267         clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
 268         clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
 269         clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
 270         clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
 271         clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
 272         clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
 273         clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
 274         clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
 275         clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
 276         clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
 277         clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
 278         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 279         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
 280         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
 281         clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
 282         clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
 283         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
 284         clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
 285         clk_register_clkdev(clk[iim_gate], "iim", NULL);
 286         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
 287         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
 288         clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
 289         clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
 290         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
 291         clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
 292         clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
 293         clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
 294         clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
 295         clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
 296
 297         /* Set SDHC parents to be PLL2 */
 298         clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
 299         clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
 300
 301         /* move usb phy clk to 24MHz */
 302         clk_set_parent(clk[usb_phy_sel], clk[osc]);
 303
 304         clk_prepare_enable(clk[gpc_dvfs]);
 305         clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
 306         clk_prepare_enable(clk[aips_tz1]);
 307         clk_prepare_enable(clk[aips_tz2]); /* fec */
 308         clk_prepare_enable(clk[spba]);
 309         clk_prepare_enable(clk[emi_fast_gate]); /* fec */
 310         clk_prepare_enable(clk[emi_slow_gate]); /* eim */
 311         clk_prepare_enable(clk[mipi_hsc1_gate]);
 312         clk_prepare_enable(clk[mipi_hsc2_gate]);
 313         clk_prepare_enable(clk[mipi_esc_gate]);
 314         clk_prepare_enable(clk[mipi_hsp_gate]);
 315         clk_prepare_enable(clk[tmax1]);
 316         clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
 317         clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
 318 }
 319
 320 int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 321                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 322 {
 323         int i;
 324         u32 val;
 325         struct device_node *np;
 326
 327         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
 328         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
 329         clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
 330         clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
 331                                 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
 332         clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
 333                                 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
 334         clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
 335                                 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
 336         clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
 337         clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
 338         clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 339         clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
 340         clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
 341         clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 342         clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
 343         clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
 344         clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
 345         clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
 346         clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
 347         clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
 348
 349         for (i = 0; i < ARRAY_SIZE(clk); i++)
 350                 if (IS_ERR(clk[i]))
 351                         pr_err("i.MX51 clk %d: register failed with %ld\n",
 352                                 i, PTR_ERR(clk[i]));
 353
 354         np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
 355         clk_data.clks = clk;
 356         clk_data.clk_num = ARRAY_SIZE(clk);
 357         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 358
 359         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 360
 361         clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
 362         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
 363         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
 364         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
 365         clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
 366         clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
 367         clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
 368         clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
 369         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
 370         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
 371         clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
 372         clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
 373         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
 374         clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
 375         clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
 376         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
 377         clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
 378         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
 379         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
 380         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
 381
 382         /* set the usboh3 parent to pll2_sw */
 383         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
 384
 385         /* set SDHC root clock to 166.25MHZ*/
 386         clk_set_rate(clk[esdhc_a_podf], 166250000);
 387         clk_set_rate(clk[esdhc_b_podf], 166250000);
 388
 389         /* System timer */
 390         mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
 391
 392         clk_prepare_enable(clk[iim_gate]);
 393         imx_print_silicon_rev("i.MX51", mx51_revision());
 394         clk_disable_unprepare(clk[iim_gate]);
 395
 396         /*
 397          * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
 398          * longer supported. Set to one for better power saving.
 399          *
 400          * The effect of not setting these bits is that MIPI clocks can't be
 401          * enabled without the IPU clock being enabled aswell.
 402          */
 403         val = readl(MXC_CCM_CCDR);
 404         val |= 1 << 18;
 405         writel(val, MXC_CCM_CCDR);
 406
 407         val = readl(MXC_CCM_CLPCR);
 408         val |= 1 << 23;
 409         writel(val, MXC_CCM_CLPCR);
 410
 411         return 0;
 412 }
 413
 414 int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 415                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 416 {
 417         int i;
 418         unsigned long r;
 419         struct device_node *np;
 420
 421         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
 422         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
 423         clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
 424         clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
 425
 426         clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
 427                                 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
 428         clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
 429         clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
 430         clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
 431         clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
 432                                 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
 433         clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
 434         clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
 435         clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
 436         clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
 437         clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
 438                                 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
 439         clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
 440                                 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
 441         clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
 442                                 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
 443         clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
 444         clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
 445         clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 446         clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
 447         clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
 448         clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 449         clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
 450         clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
 451         clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
 452                                 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
 453         clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
 454         clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
 455         clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
 456         clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
 457         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
 458
 459         for (i = 0; i < ARRAY_SIZE(clk); i++)
 460                 if (IS_ERR(clk[i]))
 461                         pr_err("i.MX53 clk %d: register failed with %ld\n",
 462                                 i, PTR_ERR(clk[i]));
 463
 464         np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
 465         clk_data.clks = clk;
 466         clk_data.clk_num = ARRAY_SIZE(clk);
 467         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 468
 469         mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
 470
 471         clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
 472         clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
 473         clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
 474         clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
 475         clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
 476         clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
 477         clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
 478         clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
 479         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
 480         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
 481         clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
 482         clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
 483         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
 484         clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
 485         clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
 486         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
 487         clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
 488         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
 489         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
 490         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
 491
 492         /* set SDHC root clock to 200MHZ*/
 493         clk_set_rate(clk[esdhc_a_podf], 200000000);
 494         clk_set_rate(clk[esdhc_b_podf], 200000000);
 495
 496         /* System timer */
 497         mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
 498
 499         clk_prepare_enable(clk[iim_gate]);
 500         imx_print_silicon_rev("i.MX53", mx53_revision());
 501         clk_disable_unprepare(clk[iim_gate]);
 502
 503         r = clk_round_rate(clk[usboh3_per_gate], 54000000);
 504         clk_set_rate(clk[usboh3_per_gate], r);
 505
 506         return 0;
 507 }
 508
 509 #ifdef CONFIG_OF
 510 static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
 511                                    unsigned long *ckih1, unsigned long *ckih2)
 512 {
 513         struct device_node *np;
 514
 515         /* retrieve the freqency of fixed clocks from device tree */
 516         for_each_compatible_node(np, NULL, "fixed-clock") {
 517                 u32 rate;
 518                 if (of_property_read_u32(np, "clock-frequency", &rate))
 519                         continue;
 520
 521                 if (of_device_is_compatible(np, "fsl,imx-ckil"))
 522                         *ckil = rate;
 523                 else if (of_device_is_compatible(np, "fsl,imx-osc"))
 524                         *osc = rate;
 525                 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
 526                         *ckih1 = rate;
 527                 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
 528                         *ckih2 = rate;
 529         }
 530 }
 531
 532 int __init mx51_clocks_init_dt(void)
 533 {
 534         unsigned long ckil, osc, ckih1, ckih2;
 535
 536         clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
 537         return mx51_clocks_init(ckil, osc, ckih1, ckih2);
 538 }
 539
 540 int __init mx53_clocks_init_dt(void)
 541 {
 542         unsigned long ckil, osc, ckih1, ckih2;
 543
 544         clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
 545         return mx53_clocks_init(ckil, osc, ckih1, ckih2);
 546 }
 547 #endif