arch/arm/mach-imx/clk-pllv1.c

   1 #include <linux/clk.h>
   2 #include <linux/clk-provider.h>
   3 #include <linux/io.h>
   4 #include <linux/slab.h>
   5 #include <linux/kernel.h>
   6 #include <linux/err.h>
   7
   8 #include "clk.h"
   9 #include "common.h"
  10 #include "hardware.h"
  11
  12 /**
  13  * pll v1
  14  *
  15  * @clk_hw      clock source
  16  * @parent      the parent clock name
  17  * @base        base address of pll registers
  18  *
  19  * PLL clock version 1, found on i.MX1/21/25/27/31/35
  20  */
  21
  22 #define MFN_BITS        (10)
  23 #define MFN_SIGN        (BIT(MFN_BITS - 1))
  24 #define MFN_MASK        (MFN_SIGN - 1)
  25
  26 struct clk_pllv1 {
  27         struct clk_hw   hw;
  28         void __iomem    *base;
  29         enum imx_pllv1_type type;
  30 };
  31
  32 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
  33
  34 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)
  35 {
  36         return pll->type == IMX_PLLV1_IMX1;
  37 }
  38
  39 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)
  40 {
  41         return pll->type == IMX_PLLV1_IMX21;
  42 }
  43
  44 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)
  45 {
  46         return pll->type == IMX_PLLV1_IMX27;
  47 }
  48
  49 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)
  50 {
  51         return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);
  52 }
  53
  54 static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
  55                 unsigned long parent_rate)
  56 {
  57         struct clk_pllv1 *pll = to_clk_pllv1(hw);
  58         long long ll;
  59         int mfn_abs;
  60         unsigned int mfi, mfn, mfd, pd;
  61         u32 reg;
  62         unsigned long rate;
  63
  64         reg = readl(pll->base);
  65
  66         /*
  67          * Get the resulting clock rate from a PLL register value and the input
  68          * frequency. PLLs with this register layout can be found on i.MX1,
  69          * i.MX21, i.MX27 and i,MX31
  70          *
  71          *                  mfi + mfn / (mfd + 1)
  72          *  f = 2 * f_ref * --------------------
  73          *                        pd + 1
  74          */
  75
  76         mfi = (reg >> 10) & 0xf;
  77         mfn = reg & 0x3ff;
  78         mfd = (reg >> 16) & 0x3ff;
  79         pd =  (reg >> 26) & 0xf;
  80
  81         mfi = mfi <= 5 ? 5 : mfi;
  82
  83         mfn_abs = mfn;
  84
  85         /*
  86          * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
  87          * 2's complements number.
  88          * On i.MX27 the bit 9 is the sign bit.
  89          */
  90         if (mfn_is_negative(pll, mfn)) {
  91                 if (is_imx27_pllv1(pll))
  92                         mfn_abs = mfn & MFN_MASK;
  93                 else
  94                         mfn_abs = BIT(MFN_BITS) - mfn;
  95         }
  96
  97         rate = parent_rate * 2;
  98         rate /= pd + 1;
  99
 100         ll = (unsigned long long)rate * mfn_abs;
 101
 102         do_div(ll, mfd + 1);
 103
 104         if (mfn_is_negative(pll, mfn))
 105                 ll = -ll;
 106
 107         ll = (rate * mfi) + ll;
 108
 109         return ll;
 110 }
 111
 112 static struct clk_ops clk_pllv1_ops = {
 113         .recalc_rate = clk_pllv1_recalc_rate,
 114 };
 115
 116 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
 117                 const char *parent, void __iomem *base)
 118 {
 119         struct clk_pllv1 *pll;
 120         struct clk *clk;
 121         struct clk_init_data init;
 122
 123         pll = kmalloc(sizeof(*pll), GFP_KERNEL);
 124         if (!pll)
 125                 return ERR_PTR(-ENOMEM);
 126
 127         pll->base = base;
 128         pll->type = type;
 129
 130         init.name = name;
 131         init.ops = &clk_pllv1_ops;
 132         init.flags = 0;
 133         init.parent_names = &parent;
 134         init.num_parents = 1;
 135
 136         pll->hw.init = &init;
 137
 138         clk = clk_register(NULL, &pll->hw);
 139         if (IS_ERR(clk))
 140                 kfree(pll);
 141
 142         return clk;
 143 }