arch/arm/mach-imx/clk-pllv2.c

   1 #include <linux/kernel.h>
   2 #include <linux/clk.h>
   3 #include <linux/io.h>
   4 #include <linux/errno.h>
   5 #include <linux/delay.h>
   6 #include <linux/slab.h>
   7 #include <linux/err.h>
   8
   9 #include <asm/div64.h>
  10
  11 #include "clk.h"
  12
  13 #define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
  14
  15 /* PLL Register Offsets */
  16 #define MXC_PLL_DP_CTL                  0x00
  17 #define MXC_PLL_DP_CONFIG               0x04
  18 #define MXC_PLL_DP_OP                   0x08
  19 #define MXC_PLL_DP_MFD                  0x0C
  20 #define MXC_PLL_DP_MFN                  0x10
  21 #define MXC_PLL_DP_MFNMINUS             0x14
  22 #define MXC_PLL_DP_MFNPLUS              0x18
  23 #define MXC_PLL_DP_HFS_OP               0x1C
  24 #define MXC_PLL_DP_HFS_MFD              0x20
  25 #define MXC_PLL_DP_HFS_MFN              0x24
  26 #define MXC_PLL_DP_MFN_TOGC             0x28
  27 #define MXC_PLL_DP_DESTAT               0x2c
  28
  29 /* PLL Register Bit definitions */
  30 #define MXC_PLL_DP_CTL_MUL_CTRL         0x2000
  31 #define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
  32 #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET  12
  33 #define MXC_PLL_DP_CTL_ADE              0x800
  34 #define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
  35 #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
  36 #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET       8
  37 #define MXC_PLL_DP_CTL_HFSM             0x80
  38 #define MXC_PLL_DP_CTL_PRE              0x40
  39 #define MXC_PLL_DP_CTL_UPEN             0x20
  40 #define MXC_PLL_DP_CTL_RST              0x10
  41 #define MXC_PLL_DP_CTL_RCP              0x8
  42 #define MXC_PLL_DP_CTL_PLM              0x4
  43 #define MXC_PLL_DP_CTL_BRM0             0x2
  44 #define MXC_PLL_DP_CTL_LRF              0x1
  45
  46 #define MXC_PLL_DP_CONFIG_BIST          0x8
  47 #define MXC_PLL_DP_CONFIG_SJC_CE        0x4
  48 #define MXC_PLL_DP_CONFIG_AREN          0x2
  49 #define MXC_PLL_DP_CONFIG_LDREQ         0x1
  50
  51 #define MXC_PLL_DP_OP_MFI_OFFSET        4
  52 #define MXC_PLL_DP_OP_MFI_MASK          (0xF << 4)
  53 #define MXC_PLL_DP_OP_PDF_OFFSET        0
  54 #define MXC_PLL_DP_OP_PDF_MASK          0xF
  55
  56 #define MXC_PLL_DP_MFD_OFFSET           0
  57 #define MXC_PLL_DP_MFD_MASK             0x07FFFFFF
  58
  59 #define MXC_PLL_DP_MFN_OFFSET           0x0
  60 #define MXC_PLL_DP_MFN_MASK             0x07FFFFFF
  61
  62 #define MXC_PLL_DP_MFN_TOGC_TOG_DIS     (1 << 17)
  63 #define MXC_PLL_DP_MFN_TOGC_TOG_EN      (1 << 16)
  64 #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET  0x0
  65 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK    0xFFFF
  66
  67 #define MXC_PLL_DP_DESTAT_TOG_SEL       (1 << 31)
  68 #define MXC_PLL_DP_DESTAT_MFN           0x07FFFFFF
  69
  70 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
  71
  72 struct clk_pllv2 {
  73         struct clk_hw   hw;
  74         void __iomem    *base;
  75 };
  76
  77 static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
  78                 unsigned long parent_rate)
  79 {
  80         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
  81         unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
  82         void __iomem *pllbase;
  83         s64 temp;
  84         struct clk_pllv2 *pll = to_clk_pllv2(hw);
  85
  86         pllbase = pll->base;
  87
  88         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
  89         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
  90         dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
  91
  92         if (pll_hfsm == 0) {
  93                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
  94                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
  95                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
  96         } else {
  97                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
  98                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
  99                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
 100         }
 101         pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
 102         mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
 103         mfi = (mfi <= 5) ? 5 : mfi;
 104         mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
 105         mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
 106         /* Sign extend to 32-bits */
 107         if (mfn >= 0x04000000) {
 108                 mfn |= 0xFC000000;
 109                 mfn_abs = -mfn;
 110         }
 111
 112         ref_clk = 2 * parent_rate;
 113         if (dbl != 0)
 114                 ref_clk *= 2;
 115
 116         ref_clk /= (pdf + 1);
 117         temp = (u64) ref_clk * mfn_abs;
 118         do_div(temp, mfd + 1);
 119         if (mfn < 0)
 120                 temp = -temp;
 121         temp = (ref_clk * mfi) + temp;
 122
 123         return temp;
 124 }
 125
 126 static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
 127                 unsigned long parent_rate)
 128 {
 129         struct clk_pllv2 *pll = to_clk_pllv2(hw);
 130         u32 reg;
 131         void __iomem *pllbase;
 132         long mfi, pdf, mfn, mfd = 999999;
 133         s64 temp64;
 134         unsigned long quad_parent_rate;
 135         unsigned long pll_hfsm, dp_ctl;
 136
 137         pllbase = pll->base;
 138
 139         quad_parent_rate = 4 * parent_rate;
 140         pdf = mfi = -1;
 141         while (++pdf < 16 && mfi < 5)
 142                 mfi = rate * (pdf+1) / quad_parent_rate;
 143         if (mfi > 15)
 144                 return -EINVAL;
 145         pdf--;
 146
 147         temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
 148         do_div(temp64, quad_parent_rate/1000000);
 149         mfn = (long)temp64;
 150
 151         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 152         /* use dpdck0_2 */
 153         __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
 154         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 155         if (pll_hfsm == 0) {
 156                 reg = mfi << 4 | pdf;
 157                 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
 158                 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
 159                 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
 160         } else {
 161                 reg = mfi << 4 | pdf;
 162                 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
 163                 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
 164                 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
 165         }
 166
 167         return 0;
 168 }
 169
 170 static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
 171                 unsigned long *prate)
 172 {
 173         return rate;
 174 }
 175
 176 static int clk_pllv2_prepare(struct clk_hw *hw)
 177 {
 178         struct clk_pllv2 *pll = to_clk_pllv2(hw);
 179         u32 reg;
 180         void __iomem *pllbase;
 181         int i = 0;
 182
 183         pllbase = pll->base;
 184         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 185         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 186
 187         /* Wait for lock */
 188         do {
 189                 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 190                 if (reg & MXC_PLL_DP_CTL_LRF)
 191                         break;
 192
 193                 udelay(1);
 194         } while (++i < MAX_DPLL_WAIT_TRIES);
 195
 196         if (i == MAX_DPLL_WAIT_TRIES) {
 197                 pr_err("MX5: pll locking failed\n");
 198                 return -EINVAL;
 199         }
 200
 201         return 0;
 202 }
 203
 204 static void clk_pllv2_unprepare(struct clk_hw *hw)
 205 {
 206         struct clk_pllv2 *pll = to_clk_pllv2(hw);
 207         u32 reg;
 208         void __iomem *pllbase;
 209
 210         pllbase = pll->base;
 211         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
 212         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 213 }
 214
 215 struct clk_ops clk_pllv2_ops = {
 216         .prepare = clk_pllv2_prepare,
 217         .unprepare = clk_pllv2_unprepare,
 218         .recalc_rate = clk_pllv2_recalc_rate,
 219         .round_rate = clk_pllv2_round_rate,
 220         .set_rate = clk_pllv2_set_rate,
 221 };
 222
 223 struct clk *imx_clk_pllv2(const char *name, const char *parent,
 224                 void __iomem *base)
 225 {
 226         struct clk_pllv2 *pll;
 227         struct clk *clk;
 228         struct clk_init_data init;
 229
 230         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 231         if (!pll)
 232                 return ERR_PTR(-ENOMEM);
 233
 234         pll->base = base;
 235
 236         init.name = name;
 237         init.ops = &clk_pllv2_ops;
 238         init.flags = 0;
 239         init.parent_names = &parent;
 240         init.num_parents = 1;
 241
 242         pll->hw.init = &init;
 243
 244         clk = clk_register(NULL, &pll->hw);
 245         if (IS_ERR(clk))
 246                 kfree(pll);
 247
 248         return clk;
 249 }