arch/arm/mach-imx/clk-pllv3.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2012 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/io.h>
  16 #include <linux/slab.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/err.h>
  19 #include "clk.h"
  20
  21 #define PLL_NUM_OFFSET          0x10
  22 #define PLL_DENOM_OFFSET        0x20
  23
  24 #define BM_PLL_POWER            (0x1 << 12)
  25 #define BM_PLL_ENABLE           (0x1 << 13)
  26 #define BM_PLL_BYPASS           (0x1 << 16)
  27 #define BM_PLL_LOCK             (0x1 << 31)
  28
  29 /**
  30  * struct clk_pllv3 - IMX PLL clock version 3
  31  * @clk_hw:      clock source
  32  * @base:        base address of PLL registers
  33  * @powerup_set: set POWER bit to power up the PLL
  34  * @div_mask:    mask of divider bits
  35  *
  36  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
  37  * is actually a multiplier, and always sits at bit 0.
  38  */
  39 struct clk_pllv3 {
  40         struct clk_hw   hw;
  41         void __iomem    *base;
  42         bool            powerup_set;
  43         u32             div_mask;
  44 };
  45
  46 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
  47
  48 static int clk_pllv3_prepare(struct clk_hw *hw)
  49 {
  50         struct clk_pllv3 *pll = to_clk_pllv3(hw);
  51         unsigned long timeout;
  52         u32 val;
  53
  54         val = readl_relaxed(pll->base);
  55         val &= ~BM_PLL_BYPASS;
  56         if (pll->powerup_set)
  57                 val |= BM_PLL_POWER;
  58         else
  59                 val &= ~BM_PLL_POWER;
  60         writel_relaxed(val, pll->base);
  61
  62         timeout = jiffies + msecs_to_jiffies(10);
  63         /* Wait for PLL to lock */
  64         do {
  65                 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
  66                         break;
  67                 if (time_after(jiffies, timeout))
  68                         break;
  69         } while (1);
  70
  71         if (readl_relaxed(pll->base) & BM_PLL_LOCK)
  72                 return 0;
  73         else
  74                 return -ETIMEDOUT;
  75 }
  76
  77 static void clk_pllv3_unprepare(struct clk_hw *hw)
  78 {
  79         struct clk_pllv3 *pll = to_clk_pllv3(hw);
  80         u32 val;
  81
  82         val = readl_relaxed(pll->base);
  83         val |= BM_PLL_BYPASS;
  84         if (pll->powerup_set)
  85                 val &= ~BM_PLL_POWER;
  86         else
  87                 val |= BM_PLL_POWER;
  88         writel_relaxed(val, pll->base);
  89 }
  90
  91 static int clk_pllv3_enable(struct clk_hw *hw)
  92 {
  93         struct clk_pllv3 *pll = to_clk_pllv3(hw);
  94         u32 val;
  95
  96         val = readl_relaxed(pll->base);
  97         val |= BM_PLL_ENABLE;
  98         writel_relaxed(val, pll->base);
  99
 100         return 0;
 101 }
 102
 103 static void clk_pllv3_disable(struct clk_hw *hw)
 104 {
 105         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 106         u32 val;
 107
 108         val = readl_relaxed(pll->base);
 109         val &= ~BM_PLL_ENABLE;
 110         writel_relaxed(val, pll->base);
 111 }
 112
 113 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
 114                                            unsigned long parent_rate)
 115 {
 116         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 117         u32 div = readl_relaxed(pll->base)  & pll->div_mask;
 118
 119         return (div == 1) ? parent_rate * 22 : parent_rate * 20;
 120 }
 121
 122 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
 123                                  unsigned long *prate)
 124 {
 125         unsigned long parent_rate = *prate;
 126
 127         return (rate >= parent_rate * 22) ? parent_rate * 22 :
 128                                             parent_rate * 20;
 129 }
 130
 131 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
 132                 unsigned long parent_rate)
 133 {
 134         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 135         u32 val, div;
 136
 137         if (rate == parent_rate * 22)
 138                 div = 1;
 139         else if (rate == parent_rate * 20)
 140                 div = 0;
 141         else
 142                 return -EINVAL;
 143
 144         val = readl_relaxed(pll->base);
 145         val &= ~pll->div_mask;
 146         val |= div;
 147         writel_relaxed(val, pll->base);
 148
 149         return 0;
 150 }
 151
 152 static const struct clk_ops clk_pllv3_ops = {
 153         .prepare        = clk_pllv3_prepare,
 154         .unprepare      = clk_pllv3_unprepare,
 155         .enable         = clk_pllv3_enable,
 156         .disable        = clk_pllv3_disable,
 157         .recalc_rate    = clk_pllv3_recalc_rate,
 158         .round_rate     = clk_pllv3_round_rate,
 159         .set_rate       = clk_pllv3_set_rate,
 160 };
 161
 162 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
 163                                                unsigned long parent_rate)
 164 {
 165         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 166         u32 div = readl_relaxed(pll->base) & pll->div_mask;
 167
 168         return parent_rate * div / 2;
 169 }
 170
 171 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
 172                                      unsigned long *prate)
 173 {
 174         unsigned long parent_rate = *prate;
 175         unsigned long min_rate = parent_rate * 54 / 2;
 176         unsigned long max_rate = parent_rate * 108 / 2;
 177         u32 div;
 178
 179         if (rate > max_rate)
 180                 rate = max_rate;
 181         else if (rate < min_rate)
 182                 rate = min_rate;
 183         div = rate * 2 / parent_rate;
 184
 185         return parent_rate * div / 2;
 186 }
 187
 188 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
 189                 unsigned long parent_rate)
 190 {
 191         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 192         unsigned long min_rate = parent_rate * 54 / 2;
 193         unsigned long max_rate = parent_rate * 108 / 2;
 194         u32 val, div;
 195
 196         if (rate < min_rate || rate > max_rate)
 197                 return -EINVAL;
 198
 199         div = rate * 2 / parent_rate;
 200         val = readl_relaxed(pll->base);
 201         val &= ~pll->div_mask;
 202         val |= div;
 203         writel_relaxed(val, pll->base);
 204
 205         return 0;
 206 }
 207
 208 static const struct clk_ops clk_pllv3_sys_ops = {
 209         .prepare        = clk_pllv3_prepare,
 210         .unprepare      = clk_pllv3_unprepare,
 211         .enable         = clk_pllv3_enable,
 212         .disable        = clk_pllv3_disable,
 213         .recalc_rate    = clk_pllv3_sys_recalc_rate,
 214         .round_rate     = clk_pllv3_sys_round_rate,
 215         .set_rate       = clk_pllv3_sys_set_rate,
 216 };
 217
 218 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
 219                                               unsigned long parent_rate)
 220 {
 221         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 222         u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
 223         u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
 224         u32 div = readl_relaxed(pll->base) & pll->div_mask;
 225
 226         return (parent_rate * div) + ((parent_rate / mfd) * mfn);
 227 }
 228
 229 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
 230                                     unsigned long *prate)
 231 {
 232         unsigned long parent_rate = *prate;
 233         unsigned long min_rate = parent_rate * 27;
 234         unsigned long max_rate = parent_rate * 54;
 235         u32 div;
 236         u32 mfn, mfd = 1000000;
 237         s64 temp64;
 238
 239         if (rate > max_rate)
 240                 rate = max_rate;
 241         else if (rate < min_rate)
 242                 rate = min_rate;
 243
 244         div = rate / parent_rate;
 245         temp64 = (u64) (rate - div * parent_rate);
 246         temp64 *= mfd;
 247         do_div(temp64, parent_rate);
 248         mfn = temp64;
 249
 250         return parent_rate * div + parent_rate / mfd * mfn;
 251 }
 252
 253 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
 254                 unsigned long parent_rate)
 255 {
 256         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 257         unsigned long min_rate = parent_rate * 27;
 258         unsigned long max_rate = parent_rate * 54;
 259         u32 val, div;
 260         u32 mfn, mfd = 1000000;
 261         s64 temp64;
 262
 263         if (rate < min_rate || rate > max_rate)
 264                 return -EINVAL;
 265
 266         div = rate / parent_rate;
 267         temp64 = (u64) (rate - div * parent_rate);
 268         temp64 *= mfd;
 269         do_div(temp64, parent_rate);
 270         mfn = temp64;
 271
 272         val = readl_relaxed(pll->base);
 273         val &= ~pll->div_mask;
 274         val |= div;
 275         writel_relaxed(val, pll->base);
 276         writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
 277         writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
 278
 279         return 0;
 280 }
 281
 282 static const struct clk_ops clk_pllv3_av_ops = {
 283         .prepare        = clk_pllv3_prepare,
 284         .unprepare      = clk_pllv3_unprepare,
 285         .enable         = clk_pllv3_enable,
 286         .disable        = clk_pllv3_disable,
 287         .recalc_rate    = clk_pllv3_av_recalc_rate,
 288         .round_rate     = clk_pllv3_av_round_rate,
 289         .set_rate       = clk_pllv3_av_set_rate,
 290 };
 291
 292 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
 293                                                 unsigned long parent_rate)
 294 {
 295         return 500000000;
 296 }
 297
 298 static const struct clk_ops clk_pllv3_enet_ops = {
 299         .prepare        = clk_pllv3_prepare,
 300         .unprepare      = clk_pllv3_unprepare,
 301         .enable         = clk_pllv3_enable,
 302         .disable        = clk_pllv3_disable,
 303         .recalc_rate    = clk_pllv3_enet_recalc_rate,
 304 };
 305
 306 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 307                           const char *parent_name, void __iomem *base,
 308                           u32 div_mask)
 309 {
 310         struct clk_pllv3 *pll;
 311         const struct clk_ops *ops;
 312         struct clk *clk;
 313         struct clk_init_data init;
 314
 315         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 316         if (!pll)
 317                 return ERR_PTR(-ENOMEM);
 318
 319         switch (type) {
 320         case IMX_PLLV3_SYS:
 321                 ops = &clk_pllv3_sys_ops;
 322                 break;
 323         case IMX_PLLV3_USB:
 324                 ops = &clk_pllv3_ops;
 325                 pll->powerup_set = true;
 326                 break;
 327         case IMX_PLLV3_AV:
 328                 ops = &clk_pllv3_av_ops;
 329                 break;
 330         case IMX_PLLV3_ENET:
 331                 ops = &clk_pllv3_enet_ops;
 332                 break;
 333         default:
 334                 ops = &clk_pllv3_ops;
 335         }
 336         pll->base = base;
 337         pll->div_mask = div_mask;
 338
 339         init.name = name;
 340         init.ops = ops;
 341         init.flags = 0;
 342         init.parent_names = &parent_name;
 343         init.num_parents = 1;
 344
 345         pll->hw.init = &init;
 346
 347         clk = clk_register(NULL, &pll->hw);
 348         if (IS_ERR(clk))
 349                 kfree(pll);
 350
 351         return clk;
 352 }