0c5ade48d598136ed7f84a51641df3da6f2be760
[deliverable/linux.git] / arch / arm / mach-imx / devices.c
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 * MA 02110-1301, USA.
31 */
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
39
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
43 #include <mach/mmc.h>
44
45 #include "devices.h"
46
47 #if defined(CONFIG_ARCH_MX1)
48 /* GPIO port description */
49 static struct mxc_gpio_port imx_gpio_ports[] = {
50 {
51 .chip.label = "gpio-0",
52 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
53 .irq = MX1_GPIO_INT_PORTA,
54 .virtual_irq_start = MXC_GPIO_IRQ_START,
55 }, {
56 .chip.label = "gpio-1",
57 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
58 .irq = MX1_GPIO_INT_PORTB,
59 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
60 }, {
61 .chip.label = "gpio-2",
62 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
63 .irq = MX1_GPIO_INT_PORTC,
64 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
65 }, {
66 .chip.label = "gpio-3",
67 .base = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
68 .irq = MX1_GPIO_INT_PORTD,
69 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
70 }
71 };
72
73 int __init imx1_register_gpios(void)
74 {
75 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
76 }
77 #endif
78
79 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
80 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
81 static struct resource mxc_wdt_resources[] = {
82 {
83 .start = MX2x_WDOG_BASE_ADDR,
84 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 };
88
89 struct platform_device mxc_wdt = {
90 .name = "imx2-wdt",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
93 .resource = mxc_wdt_resources,
94 };
95
96 /*
97 * lcdc:
98 * - i.MX1: the basic controller
99 * - i.MX21: to be checked
100 * - i.MX27: like i.MX1, with slightly variations
101 */
102 static struct resource mxc_fb[] = {
103 {
104 .start = MX2x_LCDC_BASE_ADDR,
105 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
106 .flags = IORESOURCE_MEM,
107 }, {
108 .start = MX2x_INT_LCDC,
109 .end = MX2x_INT_LCDC,
110 .flags = IORESOURCE_IRQ,
111 }
112 };
113
114 /* mxc lcd driver */
115 struct platform_device mxc_fb_device = {
116 .name = "imx-fb",
117 .id = 0,
118 .num_resources = ARRAY_SIZE(mxc_fb),
119 .resource = mxc_fb,
120 .dev = {
121 .coherent_dma_mask = DMA_BIT_MASK(32),
122 },
123 };
124
125 static struct resource mxc_pwm_resources[] = {
126 {
127 .start = MX2x_PWM_BASE_ADDR,
128 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
129 .flags = IORESOURCE_MEM,
130 }, {
131 .start = MX2x_INT_PWM,
132 .end = MX2x_INT_PWM,
133 .flags = IORESOURCE_IRQ,
134 }
135 };
136
137 struct platform_device mxc_pwm_device = {
138 .name = "mxc_pwm",
139 .id = 0,
140 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
141 .resource = mxc_pwm_resources,
142 };
143
144 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
145 static struct resource mxc_sdhc_resources ## n[] = { \
146 { \
147 .start = baseaddr, \
148 .end = baseaddr + SZ_4K - 1, \
149 .flags = IORESOURCE_MEM, \
150 }, { \
151 .start = irq, \
152 .end = irq, \
153 .flags = IORESOURCE_IRQ, \
154 }, { \
155 .start = dmareq, \
156 .end = dmareq, \
157 .flags = IORESOURCE_DMA, \
158 }, \
159 }; \
160 \
161 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
162 \
163 struct platform_device mxc_sdhc_device ## n = { \
164 .name = "mxc-mmc", \
165 .id = n, \
166 .dev = { \
167 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
168 .coherent_dma_mask = DMA_BIT_MASK(32), \
169 }, \
170 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
171 .resource = mxc_sdhc_resources ## n, \
172 }
173
174 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
175 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
176
177 #ifdef CONFIG_MACH_MX27
178 static struct resource otg_resources[] = {
179 {
180 .start = MX27_USBOTG_BASE_ADDR,
181 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
182 .flags = IORESOURCE_MEM,
183 }, {
184 .start = MX27_INT_USB3,
185 .end = MX27_INT_USB3,
186 .flags = IORESOURCE_IRQ,
187 },
188 };
189
190 static u64 otg_dmamask = DMA_BIT_MASK(32);
191
192 /* OTG gadget device */
193 struct platform_device mxc_otg_udc_device = {
194 .name = "fsl-usb2-udc",
195 .id = -1,
196 .dev = {
197 .dma_mask = &otg_dmamask,
198 .coherent_dma_mask = DMA_BIT_MASK(32),
199 },
200 .resource = otg_resources,
201 .num_resources = ARRAY_SIZE(otg_resources),
202 };
203
204 /* OTG host */
205 struct platform_device mxc_otg_host = {
206 .name = "mxc-ehci",
207 .id = 0,
208 .dev = {
209 .coherent_dma_mask = DMA_BIT_MASK(32),
210 .dma_mask = &otg_dmamask,
211 },
212 .resource = otg_resources,
213 .num_resources = ARRAY_SIZE(otg_resources),
214 };
215
216 /* USB host 1 */
217
218 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
219
220 static struct resource mxc_usbh1_resources[] = {
221 {
222 .start = MX27_USBOTG_BASE_ADDR + 0x200,
223 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
224 .flags = IORESOURCE_MEM,
225 }, {
226 .start = MX27_INT_USB1,
227 .end = MX27_INT_USB1,
228 .flags = IORESOURCE_IRQ,
229 },
230 };
231
232 struct platform_device mxc_usbh1 = {
233 .name = "mxc-ehci",
234 .id = 1,
235 .dev = {
236 .coherent_dma_mask = DMA_BIT_MASK(32),
237 .dma_mask = &usbh1_dmamask,
238 },
239 .resource = mxc_usbh1_resources,
240 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
241 };
242
243 /* USB host 2 */
244 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
245
246 static struct resource mxc_usbh2_resources[] = {
247 {
248 .start = MX27_USBOTG_BASE_ADDR + 0x400,
249 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
250 .flags = IORESOURCE_MEM,
251 }, {
252 .start = MX27_INT_USB2,
253 .end = MX27_INT_USB2,
254 .flags = IORESOURCE_IRQ,
255 },
256 };
257
258 struct platform_device mxc_usbh2 = {
259 .name = "mxc-ehci",
260 .id = 2,
261 .dev = {
262 .coherent_dma_mask = DMA_BIT_MASK(32),
263 .dma_mask = &usbh2_dmamask,
264 },
265 .resource = mxc_usbh2_resources,
266 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
267 };
268 #endif
269
270 /* GPIO port description */
271 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
272 { \
273 .chip.label = "gpio-" #n, \
274 .irq = _irq, \
275 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
276 n * 0x100), \
277 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
278 }
279
280 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
281 { \
282 .chip.label = "gpio-" #n, \
283 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
284 n * 0x100), \
285 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
286 }
287
288 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
289 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
290 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
291 DEFINE_MXC_GPIO_PORT(SOC, 1), \
292 DEFINE_MXC_GPIO_PORT(SOC, 2), \
293 DEFINE_MXC_GPIO_PORT(SOC, 3), \
294 DEFINE_MXC_GPIO_PORT(SOC, 4), \
295 DEFINE_MXC_GPIO_PORT(SOC, 5), \
296 }
297
298 #ifdef CONFIG_MACH_MX21
299 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
300
301 int __init imx21_register_gpios(void)
302 {
303 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
304 }
305 #endif
306
307 #ifdef CONFIG_MACH_MX27
308 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
309
310 int __init imx27_register_gpios(void)
311 {
312 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
313 }
314 #endif
315
316 #ifdef CONFIG_MACH_MX21
317 static struct resource mx21_usbhc_resources[] = {
318 {
319 .start = MX21_USBOTG_BASE_ADDR,
320 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .start = MX21_INT_USBHOST,
325 .end = MX21_INT_USBHOST,
326 .flags = IORESOURCE_IRQ,
327 },
328 };
329
330 struct platform_device mx21_usbhc_device = {
331 .name = "imx21-hcd",
332 .id = 0,
333 .dev = {
334 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
335 .coherent_dma_mask = DMA_BIT_MASK(32),
336 },
337 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
338 .resource = mx21_usbhc_resources,
339 };
340 #endif
341
342 static struct resource imx_kpp_resources[] = {
343 {
344 .start = MX2x_KPP_BASE_ADDR,
345 .end = MX2x_KPP_BASE_ADDR + 0xf,
346 .flags = IORESOURCE_MEM
347 }, {
348 .start = MX2x_INT_KPP,
349 .end = MX2x_INT_KPP,
350 .flags = IORESOURCE_IRQ,
351 },
352 };
353
354 struct platform_device imx_kpp_device = {
355 .name = "imx-keypad",
356 .id = -1,
357 .num_resources = ARRAY_SIZE(imx_kpp_resources),
358 .resource = imx_kpp_resources,
359 };
360
361 #endif
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