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[deliverable/linux.git] / arch / arm / mach-imx / devices.c
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 * MA 02110-1301, USA.
28 */
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/serial.h>
36
37 #include <mach/irqs.h>
38 #include <mach/hardware.h>
39 #include <mach/common.h>
40 #include <mach/mmc.h>
41
42 #include "devices.h"
43
44 /*
45 * SPI master controller
46 *
47 * - i.MX1: 2 channel (slighly different register setting)
48 * - i.MX21: 2 channel
49 * - i.MX27: 3 channel
50 */
51 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
52 static struct resource mxc_spi_resources ## n[] = { \
53 { \
54 .start = baseaddr, \
55 .end = baseaddr + SZ_4K - 1, \
56 .flags = IORESOURCE_MEM, \
57 }, { \
58 .start = irq, \
59 .end = irq, \
60 .flags = IORESOURCE_IRQ, \
61 }, \
62 }; \
63 \
64 struct platform_device mxc_spi_device ## n = { \
65 .name = "spi_imx", \
66 .id = n, \
67 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
68 .resource = mxc_spi_resources ## n, \
69 }
70
71 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
72 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
73
74 #ifdef CONFIG_MACH_MX27
75 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
76 #endif
77
78 /*
79 * General Purpose Timer
80 * - i.MX21: 3 timers
81 * - i.MX27: 6 timers
82 */
83 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
84 static struct resource timer ## n ##_resources[] = { \
85 { \
86 .start = baseaddr, \
87 .end = baseaddr + SZ_4K - 1, \
88 .flags = IORESOURCE_MEM, \
89 }, { \
90 .start = irq, \
91 .end = irq, \
92 .flags = IORESOURCE_IRQ, \
93 } \
94 }; \
95 \
96 struct platform_device mxc_gpt ## n = { \
97 .name = "imx_gpt", \
98 .id = n, \
99 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
100 .resource = timer ## n ## _resources, \
101 }
102
103 /* We use gpt1 as system timer, so do not add a device for this one */
104 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
105 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
106
107 #ifdef CONFIG_MACH_MX27
108 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
109 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
110 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
111 #endif
112
113 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
114 static struct resource mxc_wdt_resources[] = {
115 {
116 .start = MX2x_WDOG_BASE_ADDR,
117 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 };
121
122 struct platform_device mxc_wdt = {
123 .name = "imx2-wdt",
124 .id = 0,
125 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
126 .resource = mxc_wdt_resources,
127 };
128
129 static struct resource mxc_w1_master_resources[] = {
130 {
131 .start = MX2x_OWIRE_BASE_ADDR,
132 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
133 .flags = IORESOURCE_MEM,
134 },
135 };
136
137 struct platform_device mxc_w1_master_device = {
138 .name = "mxc_w1",
139 .id = 0,
140 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
141 .resource = mxc_w1_master_resources,
142 };
143
144 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
145 static struct resource pfx ## _nand_resources[] = { \
146 { \
147 .start = baseaddr, \
148 .end = baseaddr + SZ_4K - 1, \
149 .flags = IORESOURCE_MEM, \
150 }, { \
151 .start = irq, \
152 .end = irq, \
153 .flags = IORESOURCE_IRQ, \
154 }, \
155 }; \
156 \
157 struct platform_device pfx ## _nand_device = { \
158 .name = "mxc_nand", \
159 .id = 0, \
160 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
161 .resource = pfx ## _nand_resources, \
162 }
163
164 #ifdef CONFIG_MACH_MX21
165 DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
166 #endif
167
168 #ifdef CONFIG_MACH_MX27
169 DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
170 #endif
171
172 /*
173 * lcdc:
174 * - i.MX1: the basic controller
175 * - i.MX21: to be checked
176 * - i.MX27: like i.MX1, with slightly variations
177 */
178 static struct resource mxc_fb[] = {
179 {
180 .start = MX2x_LCDC_BASE_ADDR,
181 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
182 .flags = IORESOURCE_MEM,
183 }, {
184 .start = MX2x_INT_LCDC,
185 .end = MX2x_INT_LCDC,
186 .flags = IORESOURCE_IRQ,
187 }
188 };
189
190 /* mxc lcd driver */
191 struct platform_device mxc_fb_device = {
192 .name = "imx-fb",
193 .id = 0,
194 .num_resources = ARRAY_SIZE(mxc_fb),
195 .resource = mxc_fb,
196 .dev = {
197 .coherent_dma_mask = DMA_BIT_MASK(32),
198 },
199 };
200
201 #ifdef CONFIG_MACH_MX27
202 static struct resource mxc_fec_resources[] = {
203 {
204 .start = MX27_FEC_BASE_ADDR,
205 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
206 .flags = IORESOURCE_MEM,
207 }, {
208 .start = MX27_INT_FEC,
209 .end = MX27_INT_FEC,
210 .flags = IORESOURCE_IRQ,
211 },
212 };
213
214 struct platform_device mxc_fec_device = {
215 .name = "fec",
216 .id = 0,
217 .num_resources = ARRAY_SIZE(mxc_fec_resources),
218 .resource = mxc_fec_resources,
219 };
220 #endif
221
222 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
223 static struct resource mxc_i2c_resources ## n[] = { \
224 { \
225 .start = baseaddr, \
226 .end = baseaddr + SZ_4K - 1, \
227 .flags = IORESOURCE_MEM, \
228 }, { \
229 .start = irq, \
230 .end = irq, \
231 .flags = IORESOURCE_IRQ, \
232 } \
233 }; \
234 \
235 struct platform_device mxc_i2c_device ## n = { \
236 .name = "imx-i2c", \
237 .id = n, \
238 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
239 .resource = mxc_i2c_resources ## n, \
240 }
241
242 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
243
244 #ifdef CONFIG_MACH_MX27
245 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
246 #endif
247
248 static struct resource mxc_pwm_resources[] = {
249 {
250 .start = MX2x_PWM_BASE_ADDR,
251 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
252 .flags = IORESOURCE_MEM,
253 }, {
254 .start = MX2x_INT_PWM,
255 .end = MX2x_INT_PWM,
256 .flags = IORESOURCE_IRQ,
257 }
258 };
259
260 struct platform_device mxc_pwm_device = {
261 .name = "mxc_pwm",
262 .id = 0,
263 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
264 .resource = mxc_pwm_resources,
265 };
266
267 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
268 static struct resource mxc_sdhc_resources ## n[] = { \
269 { \
270 .start = baseaddr, \
271 .end = baseaddr + SZ_4K - 1, \
272 .flags = IORESOURCE_MEM, \
273 }, { \
274 .start = irq, \
275 .end = irq, \
276 .flags = IORESOURCE_IRQ, \
277 }, { \
278 .start = dmareq, \
279 .end = dmareq, \
280 .flags = IORESOURCE_DMA, \
281 }, \
282 }; \
283 \
284 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
285 \
286 struct platform_device mxc_sdhc_device ## n = { \
287 .name = "mxc-mmc", \
288 .id = n, \
289 .dev = { \
290 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
291 .coherent_dma_mask = DMA_BIT_MASK(32), \
292 }, \
293 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
294 .resource = mxc_sdhc_resources ## n, \
295 }
296
297 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
298 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
299
300 #ifdef CONFIG_MACH_MX27
301 static struct resource otg_resources[] = {
302 {
303 .start = MX27_USBOTG_BASE_ADDR,
304 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
305 .flags = IORESOURCE_MEM,
306 }, {
307 .start = MX27_INT_USB3,
308 .end = MX27_INT_USB3,
309 .flags = IORESOURCE_IRQ,
310 },
311 };
312
313 static u64 otg_dmamask = DMA_BIT_MASK(32);
314
315 /* OTG gadget device */
316 struct platform_device mxc_otg_udc_device = {
317 .name = "fsl-usb2-udc",
318 .id = -1,
319 .dev = {
320 .dma_mask = &otg_dmamask,
321 .coherent_dma_mask = DMA_BIT_MASK(32),
322 },
323 .resource = otg_resources,
324 .num_resources = ARRAY_SIZE(otg_resources),
325 };
326
327 /* OTG host */
328 struct platform_device mxc_otg_host = {
329 .name = "mxc-ehci",
330 .id = 0,
331 .dev = {
332 .coherent_dma_mask = DMA_BIT_MASK(32),
333 .dma_mask = &otg_dmamask,
334 },
335 .resource = otg_resources,
336 .num_resources = ARRAY_SIZE(otg_resources),
337 };
338
339 /* USB host 1 */
340
341 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
342
343 static struct resource mxc_usbh1_resources[] = {
344 {
345 .start = MX27_USBOTG_BASE_ADDR + 0x200,
346 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
347 .flags = IORESOURCE_MEM,
348 }, {
349 .start = MX27_INT_USB1,
350 .end = MX27_INT_USB1,
351 .flags = IORESOURCE_IRQ,
352 },
353 };
354
355 struct platform_device mxc_usbh1 = {
356 .name = "mxc-ehci",
357 .id = 1,
358 .dev = {
359 .coherent_dma_mask = DMA_BIT_MASK(32),
360 .dma_mask = &usbh1_dmamask,
361 },
362 .resource = mxc_usbh1_resources,
363 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
364 };
365
366 /* USB host 2 */
367 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
368
369 static struct resource mxc_usbh2_resources[] = {
370 {
371 .start = MX27_USBOTG_BASE_ADDR + 0x400,
372 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
373 .flags = IORESOURCE_MEM,
374 }, {
375 .start = MX27_INT_USB2,
376 .end = MX27_INT_USB2,
377 .flags = IORESOURCE_IRQ,
378 },
379 };
380
381 struct platform_device mxc_usbh2 = {
382 .name = "mxc-ehci",
383 .id = 2,
384 .dev = {
385 .coherent_dma_mask = DMA_BIT_MASK(32),
386 .dma_mask = &usbh2_dmamask,
387 },
388 .resource = mxc_usbh2_resources,
389 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
390 };
391 #endif
392
393 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
394 { \
395 .name = _name, \
396 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
397 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
398 .flags = IORESOURCE_DMA, \
399 }
400
401 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
402 static struct resource imx_ssi_resources ## n[] = { \
403 { \
404 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
405 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
406 .flags = IORESOURCE_MEM, \
407 }, { \
408 .start = MX2x_INT_SSI1, \
409 .end = MX2x_INT_SSI1, \
410 .flags = IORESOURCE_IRQ, \
411 }, \
412 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
413 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
414 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
415 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
416 }; \
417 \
418 struct platform_device imx_ssi_device ## n = { \
419 .name = "imx-ssi", \
420 .id = n, \
421 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
422 .resource = imx_ssi_resources ## n, \
423 }
424
425 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
426 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
427
428 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
429 static struct resource imx2x_uart_resources ## n[] = { \
430 { \
431 .start = baseaddr, \
432 .end = baseaddr + 0xb5, \
433 .flags = IORESOURCE_MEM, \
434 }, { \
435 .start = irq, \
436 .end = irq, \
437 .flags = IORESOURCE_IRQ, \
438 }, \
439 }; \
440 \
441 struct platform_device imx2x_uart_device ## n = { \
442 .name = "imx-uart", \
443 .id = n, \
444 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
445 .resource = imx2x_uart_resources ## n, \
446 }
447
448 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
449 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
450 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
451 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
452
453 #ifdef CONFIG_MACH_MX27
454 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
455 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
456 #endif
457
458 /* GPIO port description */
459 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
460 { \
461 .chip.label = "gpio-" #n, \
462 .irq = _irq, \
463 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
464 n * 0x100), \
465 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
466 }
467
468 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
469 { \
470 .chip.label = "gpio-" #n, \
471 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
472 n * 0x100), \
473 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
474 }
475
476 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
477 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
478 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
479 DEFINE_MXC_GPIO_PORT(SOC, 1), \
480 DEFINE_MXC_GPIO_PORT(SOC, 2), \
481 DEFINE_MXC_GPIO_PORT(SOC, 3), \
482 DEFINE_MXC_GPIO_PORT(SOC, 4), \
483 DEFINE_MXC_GPIO_PORT(SOC, 5), \
484 }
485
486 #ifdef CONFIG_MACH_MX21
487 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
488
489 int __init imx21_register_gpios(void)
490 {
491 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
492 }
493 #endif
494
495 #ifdef CONFIG_MACH_MX27
496 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
497
498 int __init imx27_register_gpios(void)
499 {
500 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
501 }
502 #endif
503
504 #ifdef CONFIG_MACH_MX21
505 static struct resource mx21_usbhc_resources[] = {
506 {
507 .start = MX21_USBOTG_BASE_ADDR,
508 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
509 .flags = IORESOURCE_MEM,
510 },
511 {
512 .start = MX21_INT_USBHOST,
513 .end = MX21_INT_USBHOST,
514 .flags = IORESOURCE_IRQ,
515 },
516 };
517
518 struct platform_device mx21_usbhc_device = {
519 .name = "imx21-hcd",
520 .id = 0,
521 .dev = {
522 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
523 .coherent_dma_mask = DMA_BIT_MASK(32),
524 },
525 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
526 .resource = mx21_usbhc_resources,
527 };
528 #endif
Linux kernel - Deliverables
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