2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/serial.h>
37 #include <mach/irqs.h>
38 #include <mach/hardware.h>
39 #include <mach/common.h>
45 * SPI master controller
47 * - i.MX1: 2 channel (slighly different register setting)
51 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
52 static struct resource mxc_spi_resources ## n[] = { \
55 .end = baseaddr + SZ_4K - 1, \
56 .flags = IORESOURCE_MEM, \
60 .flags = IORESOURCE_IRQ, \
64 struct platform_device mxc_spi_device ## n = { \
67 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
68 .resource = mxc_spi_resources ## n, \
71 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR
, MX2x_INT_CSPI1
);
72 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR
, MX2x_INT_CSPI2
);
74 #ifdef CONFIG_MACH_MX27
75 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR
, MX27_INT_CSPI3
);
79 * General Purpose Timer
83 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
84 static struct resource timer ## n ##_resources[] = { \
87 .end = baseaddr + SZ_4K - 1, \
88 .flags = IORESOURCE_MEM, \
92 .flags = IORESOURCE_IRQ, \
96 struct platform_device mxc_gpt ## n = { \
99 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
100 .resource = timer ## n ## _resources, \
103 /* We use gpt1 as system timer, so do not add a device for this one */
104 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR
, MX2x_INT_GPT2
);
105 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR
, MX2x_INT_GPT3
);
107 #ifdef CONFIG_MACH_MX27
108 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR
, MX27_INT_GPT4
);
109 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR
, MX27_INT_GPT5
);
110 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR
, MX27_INT_GPT6
);
113 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
114 static struct resource mxc_wdt_resources
[] = {
116 .start
= MX2x_WDOG_BASE_ADDR
,
117 .end
= MX2x_WDOG_BASE_ADDR
+ SZ_4K
- 1,
118 .flags
= IORESOURCE_MEM
,
122 struct platform_device mxc_wdt
= {
125 .num_resources
= ARRAY_SIZE(mxc_wdt_resources
),
126 .resource
= mxc_wdt_resources
,
129 static struct resource mxc_w1_master_resources
[] = {
131 .start
= MX2x_OWIRE_BASE_ADDR
,
132 .end
= MX2x_OWIRE_BASE_ADDR
+ SZ_4K
- 1,
133 .flags
= IORESOURCE_MEM
,
137 struct platform_device mxc_w1_master_device
= {
140 .num_resources
= ARRAY_SIZE(mxc_w1_master_resources
),
141 .resource
= mxc_w1_master_resources
,
144 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
145 static struct resource pfx ## _nand_resources[] = { \
148 .end = baseaddr + SZ_4K - 1, \
149 .flags = IORESOURCE_MEM, \
153 .flags = IORESOURCE_IRQ, \
157 struct platform_device pfx ## _nand_device = { \
158 .name = "mxc_nand", \
160 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
161 .resource = pfx ## _nand_resources, \
164 #ifdef CONFIG_MACH_MX21
165 DEFINE_MXC_NAND_DEVICE(imx21
, MX21_NFC_BASE_ADDR
, MX21_INT_NANDFC
);
168 #ifdef CONFIG_MACH_MX27
169 DEFINE_MXC_NAND_DEVICE(imx27
, MX27_NFC_BASE_ADDR
, MX27_INT_NANDFC
);
174 * - i.MX1: the basic controller
175 * - i.MX21: to be checked
176 * - i.MX27: like i.MX1, with slightly variations
178 static struct resource mxc_fb
[] = {
180 .start
= MX2x_LCDC_BASE_ADDR
,
181 .end
= MX2x_LCDC_BASE_ADDR
+ SZ_4K
- 1,
182 .flags
= IORESOURCE_MEM
,
184 .start
= MX2x_INT_LCDC
,
185 .end
= MX2x_INT_LCDC
,
186 .flags
= IORESOURCE_IRQ
,
191 struct platform_device mxc_fb_device
= {
194 .num_resources
= ARRAY_SIZE(mxc_fb
),
197 .coherent_dma_mask
= DMA_BIT_MASK(32),
201 #ifdef CONFIG_MACH_MX27
202 static struct resource mxc_fec_resources
[] = {
204 .start
= MX27_FEC_BASE_ADDR
,
205 .end
= MX27_FEC_BASE_ADDR
+ SZ_4K
- 1,
206 .flags
= IORESOURCE_MEM
,
208 .start
= MX27_INT_FEC
,
210 .flags
= IORESOURCE_IRQ
,
214 struct platform_device mxc_fec_device
= {
217 .num_resources
= ARRAY_SIZE(mxc_fec_resources
),
218 .resource
= mxc_fec_resources
,
222 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
223 static struct resource mxc_i2c_resources ## n[] = { \
226 .end = baseaddr + SZ_4K - 1, \
227 .flags = IORESOURCE_MEM, \
231 .flags = IORESOURCE_IRQ, \
235 struct platform_device mxc_i2c_device ## n = { \
238 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
239 .resource = mxc_i2c_resources ## n, \
242 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR
, MX2x_INT_I2C
);
244 #ifdef CONFIG_MACH_MX27
245 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR
, MX27_INT_I2C2
);
248 static struct resource mxc_pwm_resources
[] = {
250 .start
= MX2x_PWM_BASE_ADDR
,
251 .end
= MX2x_PWM_BASE_ADDR
+ SZ_4K
- 1,
252 .flags
= IORESOURCE_MEM
,
254 .start
= MX2x_INT_PWM
,
256 .flags
= IORESOURCE_IRQ
,
260 struct platform_device mxc_pwm_device
= {
263 .num_resources
= ARRAY_SIZE(mxc_pwm_resources
),
264 .resource
= mxc_pwm_resources
,
267 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
268 static struct resource mxc_sdhc_resources ## n[] = { \
271 .end = baseaddr + SZ_4K - 1, \
272 .flags = IORESOURCE_MEM, \
276 .flags = IORESOURCE_IRQ, \
280 .flags = IORESOURCE_DMA, \
284 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
286 struct platform_device mxc_sdhc_device ## n = { \
290 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
291 .coherent_dma_mask = DMA_BIT_MASK(32), \
293 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
294 .resource = mxc_sdhc_resources ## n, \
297 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR
, MX2x_INT_SDHC1
, MX2x_DMA_REQ_SDHC1
);
298 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR
, MX2x_INT_SDHC2
, MX2x_DMA_REQ_SDHC2
);
300 #ifdef CONFIG_MACH_MX27
301 static struct resource otg_resources
[] = {
303 .start
= MX27_USBOTG_BASE_ADDR
,
304 .end
= MX27_USBOTG_BASE_ADDR
+ 0x1ff,
305 .flags
= IORESOURCE_MEM
,
307 .start
= MX27_INT_USB3
,
308 .end
= MX27_INT_USB3
,
309 .flags
= IORESOURCE_IRQ
,
313 static u64 otg_dmamask
= DMA_BIT_MASK(32);
315 /* OTG gadget device */
316 struct platform_device mxc_otg_udc_device
= {
317 .name
= "fsl-usb2-udc",
320 .dma_mask
= &otg_dmamask
,
321 .coherent_dma_mask
= DMA_BIT_MASK(32),
323 .resource
= otg_resources
,
324 .num_resources
= ARRAY_SIZE(otg_resources
),
328 struct platform_device mxc_otg_host
= {
332 .coherent_dma_mask
= DMA_BIT_MASK(32),
333 .dma_mask
= &otg_dmamask
,
335 .resource
= otg_resources
,
336 .num_resources
= ARRAY_SIZE(otg_resources
),
341 static u64 usbh1_dmamask
= DMA_BIT_MASK(32);
343 static struct resource mxc_usbh1_resources
[] = {
345 .start
= MX27_USBOTG_BASE_ADDR
+ 0x200,
346 .end
= MX27_USBOTG_BASE_ADDR
+ 0x3ff,
347 .flags
= IORESOURCE_MEM
,
349 .start
= MX27_INT_USB1
,
350 .end
= MX27_INT_USB1
,
351 .flags
= IORESOURCE_IRQ
,
355 struct platform_device mxc_usbh1
= {
359 .coherent_dma_mask
= DMA_BIT_MASK(32),
360 .dma_mask
= &usbh1_dmamask
,
362 .resource
= mxc_usbh1_resources
,
363 .num_resources
= ARRAY_SIZE(mxc_usbh1_resources
),
367 static u64 usbh2_dmamask
= DMA_BIT_MASK(32);
369 static struct resource mxc_usbh2_resources
[] = {
371 .start
= MX27_USBOTG_BASE_ADDR
+ 0x400,
372 .end
= MX27_USBOTG_BASE_ADDR
+ 0x5ff,
373 .flags
= IORESOURCE_MEM
,
375 .start
= MX27_INT_USB2
,
376 .end
= MX27_INT_USB2
,
377 .flags
= IORESOURCE_IRQ
,
381 struct platform_device mxc_usbh2
= {
385 .coherent_dma_mask
= DMA_BIT_MASK(32),
386 .dma_mask
= &usbh2_dmamask
,
388 .resource
= mxc_usbh2_resources
,
389 .num_resources
= ARRAY_SIZE(mxc_usbh2_resources
),
393 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
396 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
397 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
398 .flags = IORESOURCE_DMA, \
401 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
402 static struct resource imx_ssi_resources ## n[] = { \
404 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
405 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
406 .flags = IORESOURCE_MEM, \
408 .start = MX2x_INT_SSI1, \
409 .end = MX2x_INT_SSI1, \
410 .flags = IORESOURCE_IRQ, \
412 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
413 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
414 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
415 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
418 struct platform_device imx_ssi_device ## n = { \
421 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
422 .resource = imx_ssi_resources ## n, \
425 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR
, MX2x_INT_SSI1
);
426 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR
, MX2x_INT_SSI1
);
428 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
429 static struct resource imx2x_uart_resources ## n[] = { \
432 .end = baseaddr + 0xb5, \
433 .flags = IORESOURCE_MEM, \
437 .flags = IORESOURCE_IRQ, \
441 struct platform_device imx2x_uart_device ## n = { \
442 .name = "imx-uart", \
444 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
445 .resource = imx2x_uart_resources ## n, \
448 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR
, MX2x_INT_UART1
);
449 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR
, MX2x_INT_UART2
);
450 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR
, MX2x_INT_UART3
);
451 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR
, MX2x_INT_UART4
);
453 #ifdef CONFIG_MACH_MX27
454 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR
, MX27_INT_UART5
);
455 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR
, MX27_INT_UART6
);
458 /* GPIO port description */
459 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
461 .chip.label = "gpio-" #n, \
463 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
465 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
468 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
470 .chip.label = "gpio-" #n, \
471 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
473 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
476 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
477 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
478 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
479 DEFINE_MXC_GPIO_PORT(SOC, 1), \
480 DEFINE_MXC_GPIO_PORT(SOC, 2), \
481 DEFINE_MXC_GPIO_PORT(SOC, 3), \
482 DEFINE_MXC_GPIO_PORT(SOC, 4), \
483 DEFINE_MXC_GPIO_PORT(SOC, 5), \
486 #ifdef CONFIG_MACH_MX21
487 DEFINE_MXC_GPIO_PORTS(MX21
, imx21
);
489 int __init
imx21_register_gpios(void)
491 return mxc_gpio_init(imx21_gpio_ports
, ARRAY_SIZE(imx21_gpio_ports
));
495 #ifdef CONFIG_MACH_MX27
496 DEFINE_MXC_GPIO_PORTS(MX27
, imx27
);
498 int __init
imx27_register_gpios(void)
500 return mxc_gpio_init(imx27_gpio_ports
, ARRAY_SIZE(imx27_gpio_ports
));
504 #ifdef CONFIG_MACH_MX21
505 static struct resource mx21_usbhc_resources
[] = {
507 .start
= MX21_USBOTG_BASE_ADDR
,
508 .end
= MX21_USBOTG_BASE_ADDR
+ SZ_8K
- 1,
509 .flags
= IORESOURCE_MEM
,
512 .start
= MX21_INT_USBHOST
,
513 .end
= MX21_INT_USBHOST
,
514 .flags
= IORESOURCE_IRQ
,
518 struct platform_device mx21_usbhc_device
= {
522 .dma_mask
= &mx21_usbhc_device
.dev
.coherent_dma_mask
,
523 .coherent_dma_mask
= DMA_BIT_MASK(32),
525 .num_resources
= ARRAY_SIZE(mx21_usbhc_resources
),
526 .resource
= mx21_usbhc_resources
,