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ARM: imx: move mx1 support to mach-imx
[deliverable/linux.git] / arch / arm / mach-imx / devices.c
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 * MA 02110-1301, USA.
31 */
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
39
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
43 #include <mach/mmc.h>
44
45 #include "devices.h"
46
47 #if defined(CONFIG_ARCH_MX1)
48 static struct resource imx1_camera_resources[] = {
49 {
50 .start = 0x00224000,
51 .end = 0x00224010,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = MX1_CSI_INT,
55 .end = MX1_CSI_INT,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
61
62 struct platform_device imx1_camera_device = {
63 .name = "mx1-camera",
64 .id = 0, /* This is used to put cameras on this interface */
65 .dev = {
66 .dma_mask = &imx1_camera_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69 .resource = imx1_camera_resources,
70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
71 };
72
73 static struct resource imx_i2c_resources[] = {
74 {
75 .start = 0x00217000,
76 .end = 0x00217010,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX1_I2C_INT,
80 .end = MX1_I2C_INT,
81 .flags = IORESOURCE_IRQ,
82 },
83 };
84
85 struct platform_device imx_i2c_device0 = {
86 .name = "imx-i2c",
87 .id = 0,
88 .resource = imx_i2c_resources,
89 .num_resources = ARRAY_SIZE(imx_i2c_resources),
90 };
91
92 #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \
93 static struct resource imx1_uart_resources ## n[] = { \
94 { \
95 .start = baseaddr, \
96 .end = baseaddr + 0xd0, \
97 .flags = IORESOURCE_MEM, \
98 }, { \
99 .start = irqrx, \
100 .end = irqrx, \
101 .flags = IORESOURCE_IRQ, \
102 }, { \
103 .start = irqtx, \
104 .end = irqtx, \
105 .flags = IORESOURCE_IRQ, \
106 }, { \
107 .start = irqrts, \
108 .end = irqrts, \
109 .flags = IORESOURCE_IRQ, \
110 }, \
111 }; \
112 \
113 struct platform_device imx1_uart_device ## n = { \
114 .name = "imx-uart", \
115 .id = n, \
116 .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \
117 .resource = imx1_uart_resources ## n, \
118 }
119
120 DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
121 DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
122
123 static struct resource imx_rtc_resources[] = {
124 {
125 .start = 0x00204000,
126 .end = 0x00204024,
127 .flags = IORESOURCE_MEM,
128 }, {
129 .start = MX1_RTC_INT,
130 .end = MX1_RTC_INT,
131 .flags = IORESOURCE_IRQ,
132 }, {
133 .start = MX1_RTC_SAMINT,
134 .end = MX1_RTC_SAMINT,
135 .flags = IORESOURCE_IRQ,
136 },
137 };
138
139 struct platform_device imx_rtc_device = {
140 .name = "rtc-imx",
141 .id = 0,
142 .resource = imx_rtc_resources,
143 .num_resources = ARRAY_SIZE(imx_rtc_resources),
144 };
145
146 static struct resource imx_wdt_resources[] = {
147 {
148 .start = 0x00201000,
149 .end = 0x00201008,
150 .flags = IORESOURCE_MEM,
151 }, {
152 .start = MX1_WDT_INT,
153 .end = MX1_WDT_INT,
154 .flags = IORESOURCE_IRQ,
155 },
156 };
157
158 struct platform_device imx_wdt_device = {
159 .name = "imx-wdt",
160 .id = 0,
161 .resource = imx_wdt_resources,
162 .num_resources = ARRAY_SIZE(imx_wdt_resources),
163 };
164
165 static struct resource imx_usb_resources[] = {
166 {
167 .start = 0x00212000,
168 .end = 0x00212148,
169 .flags = IORESOURCE_MEM,
170 }, {
171 .start = MX1_USBD_INT0,
172 .end = MX1_USBD_INT0,
173 .flags = IORESOURCE_IRQ,
174 }, {
175 .start = MX1_USBD_INT1,
176 .end = MX1_USBD_INT1,
177 .flags = IORESOURCE_IRQ,
178 }, {
179 .start = MX1_USBD_INT2,
180 .end = MX1_USBD_INT2,
181 .flags = IORESOURCE_IRQ,
182 }, {
183 .start = MX1_USBD_INT3,
184 .end = MX1_USBD_INT3,
185 .flags = IORESOURCE_IRQ,
186 }, {
187 .start = MX1_USBD_INT4,
188 .end = MX1_USBD_INT4,
189 .flags = IORESOURCE_IRQ,
190 }, {
191 .start = MX1_USBD_INT5,
192 .end = MX1_USBD_INT5,
193 .flags = IORESOURCE_IRQ,
194 }, {
195 .start = MX1_USBD_INT6,
196 .end = MX1_USBD_INT6,
197 .flags = IORESOURCE_IRQ,
198 },
199 };
200
201 struct platform_device imx_usb_device = {
202 .name = "imx_udc",
203 .id = 0,
204 .num_resources = ARRAY_SIZE(imx_usb_resources),
205 .resource = imx_usb_resources,
206 };
207
208 /* GPIO port description */
209 static struct mxc_gpio_port imx_gpio_ports[] = {
210 {
211 .chip.label = "gpio-0",
212 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
213 .irq = MX1_GPIO_INT_PORTA,
214 .virtual_irq_start = MXC_GPIO_IRQ_START,
215 }, {
216 .chip.label = "gpio-1",
217 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
218 .irq = MX1_GPIO_INT_PORTB,
219 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
220 }, {
221 .chip.label = "gpio-2",
222 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
223 .irq = MX1_GPIO_INT_PORTC,
224 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
225 }, {
226 .chip.label = "gpio-3",
227 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
228 .irq = MX1_GPIO_INT_PORTD,
229 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
230 }
231 };
232
233 int __init imx1_register_gpios(void)
234 {
235 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
236 }
237 #endif
238
239 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
240 /*
241 * SPI master controller
242 *
243 * - i.MX1: 2 channel (slighly different register setting)
244 * - i.MX21: 2 channel
245 * - i.MX27: 3 channel
246 */
247 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
248 static struct resource mxc_spi_resources ## n[] = { \
249 { \
250 .start = baseaddr, \
251 .end = baseaddr + SZ_4K - 1, \
252 .flags = IORESOURCE_MEM, \
253 }, { \
254 .start = irq, \
255 .end = irq, \
256 .flags = IORESOURCE_IRQ, \
257 }, \
258 }; \
259 \
260 struct platform_device mxc_spi_device ## n = { \
261 .name = "spi_imx", \
262 .id = n, \
263 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
264 .resource = mxc_spi_resources ## n, \
265 }
266
267 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
268 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
269
270 #ifdef CONFIG_MACH_MX27
271 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
272 #endif
273
274 /*
275 * General Purpose Timer
276 * - i.MX21: 3 timers
277 * - i.MX27: 6 timers
278 */
279 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
280 static struct resource timer ## n ##_resources[] = { \
281 { \
282 .start = baseaddr, \
283 .end = baseaddr + SZ_4K - 1, \
284 .flags = IORESOURCE_MEM, \
285 }, { \
286 .start = irq, \
287 .end = irq, \
288 .flags = IORESOURCE_IRQ, \
289 } \
290 }; \
291 \
292 struct platform_device mxc_gpt ## n = { \
293 .name = "imx_gpt", \
294 .id = n, \
295 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
296 .resource = timer ## n ## _resources, \
297 }
298
299 /* We use gpt1 as system timer, so do not add a device for this one */
300 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
301 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
302
303 #ifdef CONFIG_MACH_MX27
304 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
305 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
306 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
307 #endif
308
309 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
310 static struct resource mxc_wdt_resources[] = {
311 {
312 .start = MX2x_WDOG_BASE_ADDR,
313 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 };
317
318 struct platform_device mxc_wdt = {
319 .name = "imx2-wdt",
320 .id = 0,
321 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
322 .resource = mxc_wdt_resources,
323 };
324
325 static struct resource mxc_w1_master_resources[] = {
326 {
327 .start = MX2x_OWIRE_BASE_ADDR,
328 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
329 .flags = IORESOURCE_MEM,
330 },
331 };
332
333 struct platform_device mxc_w1_master_device = {
334 .name = "mxc_w1",
335 .id = 0,
336 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
337 .resource = mxc_w1_master_resources,
338 };
339
340 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
341 static struct resource pfx ## _nand_resources[] = { \
342 { \
343 .start = baseaddr, \
344 .end = baseaddr + SZ_4K - 1, \
345 .flags = IORESOURCE_MEM, \
346 }, { \
347 .start = irq, \
348 .end = irq, \
349 .flags = IORESOURCE_IRQ, \
350 }, \
351 }; \
352 \
353 struct platform_device pfx ## _nand_device = { \
354 .name = "mxc_nand", \
355 .id = 0, \
356 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
357 .resource = pfx ## _nand_resources, \
358 }
359
360 #ifdef CONFIG_MACH_MX21
361 DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
362 #endif
363
364 #ifdef CONFIG_MACH_MX27
365 DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
366 #endif
367
368 /*
369 * lcdc:
370 * - i.MX1: the basic controller
371 * - i.MX21: to be checked
372 * - i.MX27: like i.MX1, with slightly variations
373 */
374 static struct resource mxc_fb[] = {
375 {
376 .start = MX2x_LCDC_BASE_ADDR,
377 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
378 .flags = IORESOURCE_MEM,
379 }, {
380 .start = MX2x_INT_LCDC,
381 .end = MX2x_INT_LCDC,
382 .flags = IORESOURCE_IRQ,
383 }
384 };
385
386 /* mxc lcd driver */
387 struct platform_device mxc_fb_device = {
388 .name = "imx-fb",
389 .id = 0,
390 .num_resources = ARRAY_SIZE(mxc_fb),
391 .resource = mxc_fb,
392 .dev = {
393 .coherent_dma_mask = DMA_BIT_MASK(32),
394 },
395 };
396
397 #ifdef CONFIG_MACH_MX27
398 static struct resource mxc_fec_resources[] = {
399 {
400 .start = MX27_FEC_BASE_ADDR,
401 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
402 .flags = IORESOURCE_MEM,
403 }, {
404 .start = MX27_INT_FEC,
405 .end = MX27_INT_FEC,
406 .flags = IORESOURCE_IRQ,
407 },
408 };
409
410 struct platform_device mxc_fec_device = {
411 .name = "fec",
412 .id = 0,
413 .num_resources = ARRAY_SIZE(mxc_fec_resources),
414 .resource = mxc_fec_resources,
415 };
416 #endif
417
418 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
419 static struct resource mxc_i2c_resources ## n[] = { \
420 { \
421 .start = baseaddr, \
422 .end = baseaddr + SZ_4K - 1, \
423 .flags = IORESOURCE_MEM, \
424 }, { \
425 .start = irq, \
426 .end = irq, \
427 .flags = IORESOURCE_IRQ, \
428 } \
429 }; \
430 \
431 struct platform_device mxc_i2c_device ## n = { \
432 .name = "imx-i2c", \
433 .id = n, \
434 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
435 .resource = mxc_i2c_resources ## n, \
436 }
437
438 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
439
440 #ifdef CONFIG_MACH_MX27
441 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
442 #endif
443
444 static struct resource mxc_pwm_resources[] = {
445 {
446 .start = MX2x_PWM_BASE_ADDR,
447 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
448 .flags = IORESOURCE_MEM,
449 }, {
450 .start = MX2x_INT_PWM,
451 .end = MX2x_INT_PWM,
452 .flags = IORESOURCE_IRQ,
453 }
454 };
455
456 struct platform_device mxc_pwm_device = {
457 .name = "mxc_pwm",
458 .id = 0,
459 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
460 .resource = mxc_pwm_resources,
461 };
462
463 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
464 static struct resource mxc_sdhc_resources ## n[] = { \
465 { \
466 .start = baseaddr, \
467 .end = baseaddr + SZ_4K - 1, \
468 .flags = IORESOURCE_MEM, \
469 }, { \
470 .start = irq, \
471 .end = irq, \
472 .flags = IORESOURCE_IRQ, \
473 }, { \
474 .start = dmareq, \
475 .end = dmareq, \
476 .flags = IORESOURCE_DMA, \
477 }, \
478 }; \
479 \
480 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
481 \
482 struct platform_device mxc_sdhc_device ## n = { \
483 .name = "mxc-mmc", \
484 .id = n, \
485 .dev = { \
486 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
487 .coherent_dma_mask = DMA_BIT_MASK(32), \
488 }, \
489 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
490 .resource = mxc_sdhc_resources ## n, \
491 }
492
493 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
494 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
495
496 #ifdef CONFIG_MACH_MX27
497 static struct resource otg_resources[] = {
498 {
499 .start = MX27_USBOTG_BASE_ADDR,
500 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
501 .flags = IORESOURCE_MEM,
502 }, {
503 .start = MX27_INT_USB3,
504 .end = MX27_INT_USB3,
505 .flags = IORESOURCE_IRQ,
506 },
507 };
508
509 static u64 otg_dmamask = DMA_BIT_MASK(32);
510
511 /* OTG gadget device */
512 struct platform_device mxc_otg_udc_device = {
513 .name = "fsl-usb2-udc",
514 .id = -1,
515 .dev = {
516 .dma_mask = &otg_dmamask,
517 .coherent_dma_mask = DMA_BIT_MASK(32),
518 },
519 .resource = otg_resources,
520 .num_resources = ARRAY_SIZE(otg_resources),
521 };
522
523 /* OTG host */
524 struct platform_device mxc_otg_host = {
525 .name = "mxc-ehci",
526 .id = 0,
527 .dev = {
528 .coherent_dma_mask = DMA_BIT_MASK(32),
529 .dma_mask = &otg_dmamask,
530 },
531 .resource = otg_resources,
532 .num_resources = ARRAY_SIZE(otg_resources),
533 };
534
535 /* USB host 1 */
536
537 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
538
539 static struct resource mxc_usbh1_resources[] = {
540 {
541 .start = MX27_USBOTG_BASE_ADDR + 0x200,
542 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
543 .flags = IORESOURCE_MEM,
544 }, {
545 .start = MX27_INT_USB1,
546 .end = MX27_INT_USB1,
547 .flags = IORESOURCE_IRQ,
548 },
549 };
550
551 struct platform_device mxc_usbh1 = {
552 .name = "mxc-ehci",
553 .id = 1,
554 .dev = {
555 .coherent_dma_mask = DMA_BIT_MASK(32),
556 .dma_mask = &usbh1_dmamask,
557 },
558 .resource = mxc_usbh1_resources,
559 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
560 };
561
562 /* USB host 2 */
563 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
564
565 static struct resource mxc_usbh2_resources[] = {
566 {
567 .start = MX27_USBOTG_BASE_ADDR + 0x400,
568 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
569 .flags = IORESOURCE_MEM,
570 }, {
571 .start = MX27_INT_USB2,
572 .end = MX27_INT_USB2,
573 .flags = IORESOURCE_IRQ,
574 },
575 };
576
577 struct platform_device mxc_usbh2 = {
578 .name = "mxc-ehci",
579 .id = 2,
580 .dev = {
581 .coherent_dma_mask = DMA_BIT_MASK(32),
582 .dma_mask = &usbh2_dmamask,
583 },
584 .resource = mxc_usbh2_resources,
585 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
586 };
587 #endif
588
589 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
590 { \
591 .name = _name, \
592 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
593 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
594 .flags = IORESOURCE_DMA, \
595 }
596
597 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
598 static struct resource imx_ssi_resources ## n[] = { \
599 { \
600 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
601 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
602 .flags = IORESOURCE_MEM, \
603 }, { \
604 .start = MX2x_INT_SSI1, \
605 .end = MX2x_INT_SSI1, \
606 .flags = IORESOURCE_IRQ, \
607 }, \
608 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
609 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
610 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
611 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
612 }; \
613 \
614 struct platform_device imx_ssi_device ## n = { \
615 .name = "imx-ssi", \
616 .id = n, \
617 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
618 .resource = imx_ssi_resources ## n, \
619 }
620
621 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
622 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
623
624 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
625 static struct resource imx2x_uart_resources ## n[] = { \
626 { \
627 .start = baseaddr, \
628 .end = baseaddr + 0xb5, \
629 .flags = IORESOURCE_MEM, \
630 }, { \
631 .start = irq, \
632 .end = irq, \
633 .flags = IORESOURCE_IRQ, \
634 }, \
635 }; \
636 \
637 struct platform_device imx2x_uart_device ## n = { \
638 .name = "imx-uart", \
639 .id = n, \
640 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
641 .resource = imx2x_uart_resources ## n, \
642 }
643
644 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
645 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
646 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
647 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
648
649 #ifdef CONFIG_MACH_MX27
650 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
651 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
652 #endif
653
654 /* GPIO port description */
655 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
656 { \
657 .chip.label = "gpio-" #n, \
658 .irq = _irq, \
659 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
660 n * 0x100), \
661 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
662 }
663
664 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
665 { \
666 .chip.label = "gpio-" #n, \
667 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
668 n * 0x100), \
669 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
670 }
671
672 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
673 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
674 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
675 DEFINE_MXC_GPIO_PORT(SOC, 1), \
676 DEFINE_MXC_GPIO_PORT(SOC, 2), \
677 DEFINE_MXC_GPIO_PORT(SOC, 3), \
678 DEFINE_MXC_GPIO_PORT(SOC, 4), \
679 DEFINE_MXC_GPIO_PORT(SOC, 5), \
680 }
681
682 #ifdef CONFIG_MACH_MX21
683 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
684
685 int __init imx21_register_gpios(void)
686 {
687 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
688 }
689 #endif
690
691 #ifdef CONFIG_MACH_MX27
692 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
693
694 int __init imx27_register_gpios(void)
695 {
696 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
697 }
698 #endif
699
700 #ifdef CONFIG_MACH_MX21
701 static struct resource mx21_usbhc_resources[] = {
702 {
703 .start = MX21_USBOTG_BASE_ADDR,
704 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
705 .flags = IORESOURCE_MEM,
706 },
707 {
708 .start = MX21_INT_USBHOST,
709 .end = MX21_INT_USBHOST,
710 .flags = IORESOURCE_IRQ,
711 },
712 };
713
714 struct platform_device mx21_usbhc_device = {
715 .name = "imx21-hcd",
716 .id = 0,
717 .dev = {
718 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
719 .coherent_dma_mask = DMA_BIT_MASK(32),
720 },
721 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
722 .resource = mx21_usbhc_resources,
723 };
724 #endif
725 #endif
Linux kernel - Deliverables
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