2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
47 #if defined(CONFIG_ARCH_MX1)
48 static struct resource imx1_camera_resources
[] = {
52 .flags
= IORESOURCE_MEM
,
56 .flags
= IORESOURCE_IRQ
,
60 static u64 imx1_camera_dmamask
= DMA_BIT_MASK(32);
62 struct platform_device imx1_camera_device
= {
64 .id
= 0, /* This is used to put cameras on this interface */
66 .dma_mask
= &imx1_camera_dmamask
,
67 .coherent_dma_mask
= DMA_BIT_MASK(32),
69 .resource
= imx1_camera_resources
,
70 .num_resources
= ARRAY_SIZE(imx1_camera_resources
),
73 static struct resource imx_i2c_resources
[] = {
77 .flags
= IORESOURCE_MEM
,
81 .flags
= IORESOURCE_IRQ
,
85 struct platform_device imx_i2c_device0
= {
88 .resource
= imx_i2c_resources
,
89 .num_resources
= ARRAY_SIZE(imx_i2c_resources
),
92 #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \
93 static struct resource imx1_uart_resources ## n[] = { \
96 .end = baseaddr + 0xd0, \
97 .flags = IORESOURCE_MEM, \
101 .flags = IORESOURCE_IRQ, \
105 .flags = IORESOURCE_IRQ, \
109 .flags = IORESOURCE_IRQ, \
113 struct platform_device imx1_uart_device ## n = { \
114 .name = "imx-uart", \
116 .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \
117 .resource = imx1_uart_resources ## n, \
120 DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR
, MX1_UART1_MINT_RX
, MX1_UART1_MINT_TX
, MX1_UART1_MINT_RTS
);
121 DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR
, MX1_UART2_MINT_RX
, MX1_UART2_MINT_TX
, MX1_UART2_MINT_RTS
);
123 static struct resource imx_rtc_resources
[] = {
127 .flags
= IORESOURCE_MEM
,
129 .start
= MX1_RTC_INT
,
131 .flags
= IORESOURCE_IRQ
,
133 .start
= MX1_RTC_SAMINT
,
134 .end
= MX1_RTC_SAMINT
,
135 .flags
= IORESOURCE_IRQ
,
139 struct platform_device imx_rtc_device
= {
142 .resource
= imx_rtc_resources
,
143 .num_resources
= ARRAY_SIZE(imx_rtc_resources
),
146 static struct resource imx_wdt_resources
[] = {
150 .flags
= IORESOURCE_MEM
,
152 .start
= MX1_WDT_INT
,
154 .flags
= IORESOURCE_IRQ
,
158 struct platform_device imx_wdt_device
= {
161 .resource
= imx_wdt_resources
,
162 .num_resources
= ARRAY_SIZE(imx_wdt_resources
),
165 static struct resource imx_usb_resources
[] = {
169 .flags
= IORESOURCE_MEM
,
171 .start
= MX1_USBD_INT0
,
172 .end
= MX1_USBD_INT0
,
173 .flags
= IORESOURCE_IRQ
,
175 .start
= MX1_USBD_INT1
,
176 .end
= MX1_USBD_INT1
,
177 .flags
= IORESOURCE_IRQ
,
179 .start
= MX1_USBD_INT2
,
180 .end
= MX1_USBD_INT2
,
181 .flags
= IORESOURCE_IRQ
,
183 .start
= MX1_USBD_INT3
,
184 .end
= MX1_USBD_INT3
,
185 .flags
= IORESOURCE_IRQ
,
187 .start
= MX1_USBD_INT4
,
188 .end
= MX1_USBD_INT4
,
189 .flags
= IORESOURCE_IRQ
,
191 .start
= MX1_USBD_INT5
,
192 .end
= MX1_USBD_INT5
,
193 .flags
= IORESOURCE_IRQ
,
195 .start
= MX1_USBD_INT6
,
196 .end
= MX1_USBD_INT6
,
197 .flags
= IORESOURCE_IRQ
,
201 struct platform_device imx_usb_device
= {
204 .num_resources
= ARRAY_SIZE(imx_usb_resources
),
205 .resource
= imx_usb_resources
,
208 /* GPIO port description */
209 static struct mxc_gpio_port imx_gpio_ports
[] = {
211 .chip
.label
= "gpio-0",
212 .base
= (void __iomem
*)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR
),
213 .irq
= MX1_GPIO_INT_PORTA
,
214 .virtual_irq_start
= MXC_GPIO_IRQ_START
,
216 .chip
.label
= "gpio-1",
217 .base
= (void __iomem
*)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR
+ 0x100),
218 .irq
= MX1_GPIO_INT_PORTB
,
219 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 32,
221 .chip
.label
= "gpio-2",
222 .base
= (void __iomem
*)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR
+ 0x200),
223 .irq
= MX1_GPIO_INT_PORTC
,
224 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 64,
226 .chip
.label
= "gpio-3",
227 .base
= (void __iomem
*)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR
+ 0x300),
228 .irq
= MX1_GPIO_INT_PORTD
,
229 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 96,
233 int __init
imx1_register_gpios(void)
235 return mxc_gpio_init(imx_gpio_ports
, ARRAY_SIZE(imx_gpio_ports
));
239 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
241 * SPI master controller
243 * - i.MX1: 2 channel (slighly different register setting)
244 * - i.MX21: 2 channel
245 * - i.MX27: 3 channel
247 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
248 static struct resource mxc_spi_resources ## n[] = { \
251 .end = baseaddr + SZ_4K - 1, \
252 .flags = IORESOURCE_MEM, \
256 .flags = IORESOURCE_IRQ, \
260 struct platform_device mxc_spi_device ## n = { \
263 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
264 .resource = mxc_spi_resources ## n, \
267 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR
, MX2x_INT_CSPI1
);
268 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR
, MX2x_INT_CSPI2
);
270 #ifdef CONFIG_MACH_MX27
271 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR
, MX27_INT_CSPI3
);
275 * General Purpose Timer
279 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
280 static struct resource timer ## n ##_resources[] = { \
283 .end = baseaddr + SZ_4K - 1, \
284 .flags = IORESOURCE_MEM, \
288 .flags = IORESOURCE_IRQ, \
292 struct platform_device mxc_gpt ## n = { \
295 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
296 .resource = timer ## n ## _resources, \
299 /* We use gpt1 as system timer, so do not add a device for this one */
300 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR
, MX2x_INT_GPT2
);
301 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR
, MX2x_INT_GPT3
);
303 #ifdef CONFIG_MACH_MX27
304 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR
, MX27_INT_GPT4
);
305 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR
, MX27_INT_GPT5
);
306 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR
, MX27_INT_GPT6
);
309 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
310 static struct resource mxc_wdt_resources
[] = {
312 .start
= MX2x_WDOG_BASE_ADDR
,
313 .end
= MX2x_WDOG_BASE_ADDR
+ SZ_4K
- 1,
314 .flags
= IORESOURCE_MEM
,
318 struct platform_device mxc_wdt
= {
321 .num_resources
= ARRAY_SIZE(mxc_wdt_resources
),
322 .resource
= mxc_wdt_resources
,
325 static struct resource mxc_w1_master_resources
[] = {
327 .start
= MX2x_OWIRE_BASE_ADDR
,
328 .end
= MX2x_OWIRE_BASE_ADDR
+ SZ_4K
- 1,
329 .flags
= IORESOURCE_MEM
,
333 struct platform_device mxc_w1_master_device
= {
336 .num_resources
= ARRAY_SIZE(mxc_w1_master_resources
),
337 .resource
= mxc_w1_master_resources
,
340 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
341 static struct resource pfx ## _nand_resources[] = { \
344 .end = baseaddr + SZ_4K - 1, \
345 .flags = IORESOURCE_MEM, \
349 .flags = IORESOURCE_IRQ, \
353 struct platform_device pfx ## _nand_device = { \
354 .name = "mxc_nand", \
356 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
357 .resource = pfx ## _nand_resources, \
360 #ifdef CONFIG_MACH_MX21
361 DEFINE_MXC_NAND_DEVICE(imx21
, MX21_NFC_BASE_ADDR
, MX21_INT_NANDFC
);
364 #ifdef CONFIG_MACH_MX27
365 DEFINE_MXC_NAND_DEVICE(imx27
, MX27_NFC_BASE_ADDR
, MX27_INT_NANDFC
);
370 * - i.MX1: the basic controller
371 * - i.MX21: to be checked
372 * - i.MX27: like i.MX1, with slightly variations
374 static struct resource mxc_fb
[] = {
376 .start
= MX2x_LCDC_BASE_ADDR
,
377 .end
= MX2x_LCDC_BASE_ADDR
+ SZ_4K
- 1,
378 .flags
= IORESOURCE_MEM
,
380 .start
= MX2x_INT_LCDC
,
381 .end
= MX2x_INT_LCDC
,
382 .flags
= IORESOURCE_IRQ
,
387 struct platform_device mxc_fb_device
= {
390 .num_resources
= ARRAY_SIZE(mxc_fb
),
393 .coherent_dma_mask
= DMA_BIT_MASK(32),
397 #ifdef CONFIG_MACH_MX27
398 static struct resource mxc_fec_resources
[] = {
400 .start
= MX27_FEC_BASE_ADDR
,
401 .end
= MX27_FEC_BASE_ADDR
+ SZ_4K
- 1,
402 .flags
= IORESOURCE_MEM
,
404 .start
= MX27_INT_FEC
,
406 .flags
= IORESOURCE_IRQ
,
410 struct platform_device mxc_fec_device
= {
413 .num_resources
= ARRAY_SIZE(mxc_fec_resources
),
414 .resource
= mxc_fec_resources
,
418 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
419 static struct resource mxc_i2c_resources ## n[] = { \
422 .end = baseaddr + SZ_4K - 1, \
423 .flags = IORESOURCE_MEM, \
427 .flags = IORESOURCE_IRQ, \
431 struct platform_device mxc_i2c_device ## n = { \
434 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
435 .resource = mxc_i2c_resources ## n, \
438 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR
, MX2x_INT_I2C
);
440 #ifdef CONFIG_MACH_MX27
441 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR
, MX27_INT_I2C2
);
444 static struct resource mxc_pwm_resources
[] = {
446 .start
= MX2x_PWM_BASE_ADDR
,
447 .end
= MX2x_PWM_BASE_ADDR
+ SZ_4K
- 1,
448 .flags
= IORESOURCE_MEM
,
450 .start
= MX2x_INT_PWM
,
452 .flags
= IORESOURCE_IRQ
,
456 struct platform_device mxc_pwm_device
= {
459 .num_resources
= ARRAY_SIZE(mxc_pwm_resources
),
460 .resource
= mxc_pwm_resources
,
463 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
464 static struct resource mxc_sdhc_resources ## n[] = { \
467 .end = baseaddr + SZ_4K - 1, \
468 .flags = IORESOURCE_MEM, \
472 .flags = IORESOURCE_IRQ, \
476 .flags = IORESOURCE_DMA, \
480 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
482 struct platform_device mxc_sdhc_device ## n = { \
486 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
487 .coherent_dma_mask = DMA_BIT_MASK(32), \
489 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
490 .resource = mxc_sdhc_resources ## n, \
493 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR
, MX2x_INT_SDHC1
, MX2x_DMA_REQ_SDHC1
);
494 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR
, MX2x_INT_SDHC2
, MX2x_DMA_REQ_SDHC2
);
496 #ifdef CONFIG_MACH_MX27
497 static struct resource otg_resources
[] = {
499 .start
= MX27_USBOTG_BASE_ADDR
,
500 .end
= MX27_USBOTG_BASE_ADDR
+ 0x1ff,
501 .flags
= IORESOURCE_MEM
,
503 .start
= MX27_INT_USB3
,
504 .end
= MX27_INT_USB3
,
505 .flags
= IORESOURCE_IRQ
,
509 static u64 otg_dmamask
= DMA_BIT_MASK(32);
511 /* OTG gadget device */
512 struct platform_device mxc_otg_udc_device
= {
513 .name
= "fsl-usb2-udc",
516 .dma_mask
= &otg_dmamask
,
517 .coherent_dma_mask
= DMA_BIT_MASK(32),
519 .resource
= otg_resources
,
520 .num_resources
= ARRAY_SIZE(otg_resources
),
524 struct platform_device mxc_otg_host
= {
528 .coherent_dma_mask
= DMA_BIT_MASK(32),
529 .dma_mask
= &otg_dmamask
,
531 .resource
= otg_resources
,
532 .num_resources
= ARRAY_SIZE(otg_resources
),
537 static u64 usbh1_dmamask
= DMA_BIT_MASK(32);
539 static struct resource mxc_usbh1_resources
[] = {
541 .start
= MX27_USBOTG_BASE_ADDR
+ 0x200,
542 .end
= MX27_USBOTG_BASE_ADDR
+ 0x3ff,
543 .flags
= IORESOURCE_MEM
,
545 .start
= MX27_INT_USB1
,
546 .end
= MX27_INT_USB1
,
547 .flags
= IORESOURCE_IRQ
,
551 struct platform_device mxc_usbh1
= {
555 .coherent_dma_mask
= DMA_BIT_MASK(32),
556 .dma_mask
= &usbh1_dmamask
,
558 .resource
= mxc_usbh1_resources
,
559 .num_resources
= ARRAY_SIZE(mxc_usbh1_resources
),
563 static u64 usbh2_dmamask
= DMA_BIT_MASK(32);
565 static struct resource mxc_usbh2_resources
[] = {
567 .start
= MX27_USBOTG_BASE_ADDR
+ 0x400,
568 .end
= MX27_USBOTG_BASE_ADDR
+ 0x5ff,
569 .flags
= IORESOURCE_MEM
,
571 .start
= MX27_INT_USB2
,
572 .end
= MX27_INT_USB2
,
573 .flags
= IORESOURCE_IRQ
,
577 struct platform_device mxc_usbh2
= {
581 .coherent_dma_mask
= DMA_BIT_MASK(32),
582 .dma_mask
= &usbh2_dmamask
,
584 .resource
= mxc_usbh2_resources
,
585 .num_resources
= ARRAY_SIZE(mxc_usbh2_resources
),
589 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
592 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
593 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
594 .flags = IORESOURCE_DMA, \
597 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
598 static struct resource imx_ssi_resources ## n[] = { \
600 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
601 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
602 .flags = IORESOURCE_MEM, \
604 .start = MX2x_INT_SSI1, \
605 .end = MX2x_INT_SSI1, \
606 .flags = IORESOURCE_IRQ, \
608 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
609 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
610 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
611 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
614 struct platform_device imx_ssi_device ## n = { \
617 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
618 .resource = imx_ssi_resources ## n, \
621 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR
, MX2x_INT_SSI1
);
622 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR
, MX2x_INT_SSI1
);
624 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
625 static struct resource imx2x_uart_resources ## n[] = { \
628 .end = baseaddr + 0xb5, \
629 .flags = IORESOURCE_MEM, \
633 .flags = IORESOURCE_IRQ, \
637 struct platform_device imx2x_uart_device ## n = { \
638 .name = "imx-uart", \
640 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
641 .resource = imx2x_uart_resources ## n, \
644 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR
, MX2x_INT_UART1
);
645 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR
, MX2x_INT_UART2
);
646 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR
, MX2x_INT_UART3
);
647 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR
, MX2x_INT_UART4
);
649 #ifdef CONFIG_MACH_MX27
650 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR
, MX27_INT_UART5
);
651 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR
, MX27_INT_UART6
);
654 /* GPIO port description */
655 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
657 .chip.label = "gpio-" #n, \
659 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
661 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
664 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
666 .chip.label = "gpio-" #n, \
667 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
669 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
672 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
673 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
674 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
675 DEFINE_MXC_GPIO_PORT(SOC, 1), \
676 DEFINE_MXC_GPIO_PORT(SOC, 2), \
677 DEFINE_MXC_GPIO_PORT(SOC, 3), \
678 DEFINE_MXC_GPIO_PORT(SOC, 4), \
679 DEFINE_MXC_GPIO_PORT(SOC, 5), \
682 #ifdef CONFIG_MACH_MX21
683 DEFINE_MXC_GPIO_PORTS(MX21
, imx21
);
685 int __init
imx21_register_gpios(void)
687 return mxc_gpio_init(imx21_gpio_ports
, ARRAY_SIZE(imx21_gpio_ports
));
691 #ifdef CONFIG_MACH_MX27
692 DEFINE_MXC_GPIO_PORTS(MX27
, imx27
);
694 int __init
imx27_register_gpios(void)
696 return mxc_gpio_init(imx27_gpio_ports
, ARRAY_SIZE(imx27_gpio_ports
));
700 #ifdef CONFIG_MACH_MX21
701 static struct resource mx21_usbhc_resources
[] = {
703 .start
= MX21_USBOTG_BASE_ADDR
,
704 .end
= MX21_USBOTG_BASE_ADDR
+ SZ_8K
- 1,
705 .flags
= IORESOURCE_MEM
,
708 .start
= MX21_INT_USBHOST
,
709 .end
= MX21_INT_USBHOST
,
710 .flags
= IORESOURCE_IRQ
,
714 struct platform_device mx21_usbhc_device
= {
718 .dma_mask
= &mx21_usbhc_device
.dev
.coherent_dma_mask
,
719 .coherent_dma_mask
= DMA_BIT_MASK(32),
721 .num_resources
= ARRAY_SIZE(mx21_usbhc_resources
),
722 .resource
= mx21_usbhc_resources
,