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ARM: imx: Change the way nand devices are registered (imx21)
[deliverable/linux.git] / arch / arm / mach-imx / devices.c
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 * MA 02110-1301, USA.
31 */
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/platform_device.h>
36 #include <linux/gpio.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/serial.h>
39
40 #include <mach/irqs.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
43 #include <mach/mmc.h>
44
45 #include "devices.h"
46
47 #if defined(CONFIG_ARCH_MX1)
48 static struct resource imx1_camera_resources[] = {
49 {
50 .start = 0x00224000,
51 .end = 0x00224010,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = MX1_CSI_INT,
55 .end = MX1_CSI_INT,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
61
62 struct platform_device imx1_camera_device = {
63 .name = "mx1-camera",
64 .id = 0, /* This is used to put cameras on this interface */
65 .dev = {
66 .dma_mask = &imx1_camera_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69 .resource = imx1_camera_resources,
70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
71 };
72
73 static struct resource imx_i2c_resources[] = {
74 {
75 .start = 0x00217000,
76 .end = 0x00217010,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX1_I2C_INT,
80 .end = MX1_I2C_INT,
81 .flags = IORESOURCE_IRQ,
82 },
83 };
84
85 struct platform_device imx_i2c_device0 = {
86 .name = "imx-i2c",
87 .id = 0,
88 .resource = imx_i2c_resources,
89 .num_resources = ARRAY_SIZE(imx_i2c_resources),
90 };
91
92 #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \
93 static struct resource imx1_uart_resources ## n[] = { \
94 { \
95 .start = baseaddr, \
96 .end = baseaddr + 0xd0, \
97 .flags = IORESOURCE_MEM, \
98 }, { \
99 .start = irqrx, \
100 .end = irqrx, \
101 .flags = IORESOURCE_IRQ, \
102 }, { \
103 .start = irqtx, \
104 .end = irqtx, \
105 .flags = IORESOURCE_IRQ, \
106 }, { \
107 .start = irqrts, \
108 .end = irqrts, \
109 .flags = IORESOURCE_IRQ, \
110 }, \
111 }; \
112 \
113 struct platform_device imx1_uart_device ## n = { \
114 .name = "imx-uart", \
115 .id = n, \
116 .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \
117 .resource = imx1_uart_resources ## n, \
118 }
119
120 DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
121 DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
122
123 static struct resource imx_rtc_resources[] = {
124 {
125 .start = 0x00204000,
126 .end = 0x00204024,
127 .flags = IORESOURCE_MEM,
128 }, {
129 .start = MX1_RTC_INT,
130 .end = MX1_RTC_INT,
131 .flags = IORESOURCE_IRQ,
132 }, {
133 .start = MX1_RTC_SAMINT,
134 .end = MX1_RTC_SAMINT,
135 .flags = IORESOURCE_IRQ,
136 },
137 };
138
139 struct platform_device imx_rtc_device = {
140 .name = "rtc-imx",
141 .id = 0,
142 .resource = imx_rtc_resources,
143 .num_resources = ARRAY_SIZE(imx_rtc_resources),
144 };
145
146 static struct resource imx_wdt_resources[] = {
147 {
148 .start = 0x00201000,
149 .end = 0x00201008,
150 .flags = IORESOURCE_MEM,
151 }, {
152 .start = MX1_WDT_INT,
153 .end = MX1_WDT_INT,
154 .flags = IORESOURCE_IRQ,
155 },
156 };
157
158 struct platform_device imx_wdt_device = {
159 .name = "imx-wdt",
160 .id = 0,
161 .resource = imx_wdt_resources,
162 .num_resources = ARRAY_SIZE(imx_wdt_resources),
163 };
164
165 static struct resource imx_usb_resources[] = {
166 {
167 .start = 0x00212000,
168 .end = 0x00212148,
169 .flags = IORESOURCE_MEM,
170 }, {
171 .start = MX1_USBD_INT0,
172 .end = MX1_USBD_INT0,
173 .flags = IORESOURCE_IRQ,
174 }, {
175 .start = MX1_USBD_INT1,
176 .end = MX1_USBD_INT1,
177 .flags = IORESOURCE_IRQ,
178 }, {
179 .start = MX1_USBD_INT2,
180 .end = MX1_USBD_INT2,
181 .flags = IORESOURCE_IRQ,
182 }, {
183 .start = MX1_USBD_INT3,
184 .end = MX1_USBD_INT3,
185 .flags = IORESOURCE_IRQ,
186 }, {
187 .start = MX1_USBD_INT4,
188 .end = MX1_USBD_INT4,
189 .flags = IORESOURCE_IRQ,
190 }, {
191 .start = MX1_USBD_INT5,
192 .end = MX1_USBD_INT5,
193 .flags = IORESOURCE_IRQ,
194 }, {
195 .start = MX1_USBD_INT6,
196 .end = MX1_USBD_INT6,
197 .flags = IORESOURCE_IRQ,
198 },
199 };
200
201 struct platform_device imx_usb_device = {
202 .name = "imx_udc",
203 .id = 0,
204 .num_resources = ARRAY_SIZE(imx_usb_resources),
205 .resource = imx_usb_resources,
206 };
207
208 /* GPIO port description */
209 static struct mxc_gpio_port imx_gpio_ports[] = {
210 {
211 .chip.label = "gpio-0",
212 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
213 .irq = MX1_GPIO_INT_PORTA,
214 .virtual_irq_start = MXC_GPIO_IRQ_START,
215 }, {
216 .chip.label = "gpio-1",
217 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
218 .irq = MX1_GPIO_INT_PORTB,
219 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
220 }, {
221 .chip.label = "gpio-2",
222 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
223 .irq = MX1_GPIO_INT_PORTC,
224 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
225 }, {
226 .chip.label = "gpio-3",
227 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
228 .irq = MX1_GPIO_INT_PORTD,
229 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
230 }
231 };
232
233 int __init imx1_register_gpios(void)
234 {
235 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
236 }
237 #endif
238
239 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
240 /*
241 * SPI master controller
242 *
243 * - i.MX1: 2 channel (slighly different register setting)
244 * - i.MX21: 2 channel
245 * - i.MX27: 3 channel
246 */
247 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
248 static struct resource mxc_spi_resources ## n[] = { \
249 { \
250 .start = baseaddr, \
251 .end = baseaddr + SZ_4K - 1, \
252 .flags = IORESOURCE_MEM, \
253 }, { \
254 .start = irq, \
255 .end = irq, \
256 .flags = IORESOURCE_IRQ, \
257 }, \
258 }; \
259 \
260 struct platform_device mxc_spi_device ## n = { \
261 .name = "spi_imx", \
262 .id = n, \
263 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
264 .resource = mxc_spi_resources ## n, \
265 }
266
267 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
268 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
269
270 #ifdef CONFIG_MACH_MX27
271 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
272 #endif
273
274 /*
275 * General Purpose Timer
276 * - i.MX21: 3 timers
277 * - i.MX27: 6 timers
278 */
279 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
280 static struct resource timer ## n ##_resources[] = { \
281 { \
282 .start = baseaddr, \
283 .end = baseaddr + SZ_4K - 1, \
284 .flags = IORESOURCE_MEM, \
285 }, { \
286 .start = irq, \
287 .end = irq, \
288 .flags = IORESOURCE_IRQ, \
289 } \
290 }; \
291 \
292 struct platform_device mxc_gpt ## n = { \
293 .name = "imx_gpt", \
294 .id = n, \
295 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
296 .resource = timer ## n ## _resources, \
297 }
298
299 /* We use gpt1 as system timer, so do not add a device for this one */
300 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
301 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
302
303 #ifdef CONFIG_MACH_MX27
304 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
305 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
306 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
307 #endif
308
309 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
310 static struct resource mxc_wdt_resources[] = {
311 {
312 .start = MX2x_WDOG_BASE_ADDR,
313 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 };
317
318 struct platform_device mxc_wdt = {
319 .name = "imx2-wdt",
320 .id = 0,
321 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
322 .resource = mxc_wdt_resources,
323 };
324
325 static struct resource mxc_w1_master_resources[] = {
326 {
327 .start = MX2x_OWIRE_BASE_ADDR,
328 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
329 .flags = IORESOURCE_MEM,
330 },
331 };
332
333 struct platform_device mxc_w1_master_device = {
334 .name = "mxc_w1",
335 .id = 0,
336 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
337 .resource = mxc_w1_master_resources,
338 };
339
340 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
341 static struct resource pfx ## _nand_resources[] = { \
342 { \
343 .start = baseaddr, \
344 .end = baseaddr + SZ_4K - 1, \
345 .flags = IORESOURCE_MEM, \
346 }, { \
347 .start = irq, \
348 .end = irq, \
349 .flags = IORESOURCE_IRQ, \
350 }, \
351 }; \
352 \
353 struct platform_device pfx ## _nand_device = { \
354 .name = "mxc_nand", \
355 .id = 0, \
356 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
357 .resource = pfx ## _nand_resources, \
358 }
359
360 #ifdef CONFIG_MACH_MX27
361 DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
362 #endif
363
364 /*
365 * lcdc:
366 * - i.MX1: the basic controller
367 * - i.MX21: to be checked
368 * - i.MX27: like i.MX1, with slightly variations
369 */
370 static struct resource mxc_fb[] = {
371 {
372 .start = MX2x_LCDC_BASE_ADDR,
373 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
374 .flags = IORESOURCE_MEM,
375 }, {
376 .start = MX2x_INT_LCDC,
377 .end = MX2x_INT_LCDC,
378 .flags = IORESOURCE_IRQ,
379 }
380 };
381
382 /* mxc lcd driver */
383 struct platform_device mxc_fb_device = {
384 .name = "imx-fb",
385 .id = 0,
386 .num_resources = ARRAY_SIZE(mxc_fb),
387 .resource = mxc_fb,
388 .dev = {
389 .coherent_dma_mask = DMA_BIT_MASK(32),
390 },
391 };
392
393 #ifdef CONFIG_MACH_MX27
394 static struct resource mxc_fec_resources[] = {
395 {
396 .start = MX27_FEC_BASE_ADDR,
397 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
398 .flags = IORESOURCE_MEM,
399 }, {
400 .start = MX27_INT_FEC,
401 .end = MX27_INT_FEC,
402 .flags = IORESOURCE_IRQ,
403 },
404 };
405
406 struct platform_device mxc_fec_device = {
407 .name = "fec",
408 .id = 0,
409 .num_resources = ARRAY_SIZE(mxc_fec_resources),
410 .resource = mxc_fec_resources,
411 };
412 #endif
413
414 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
415 static struct resource mxc_i2c_resources ## n[] = { \
416 { \
417 .start = baseaddr, \
418 .end = baseaddr + SZ_4K - 1, \
419 .flags = IORESOURCE_MEM, \
420 }, { \
421 .start = irq, \
422 .end = irq, \
423 .flags = IORESOURCE_IRQ, \
424 } \
425 }; \
426 \
427 struct platform_device mxc_i2c_device ## n = { \
428 .name = "imx-i2c", \
429 .id = n, \
430 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
431 .resource = mxc_i2c_resources ## n, \
432 }
433
434 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
435
436 #ifdef CONFIG_MACH_MX27
437 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
438 #endif
439
440 static struct resource mxc_pwm_resources[] = {
441 {
442 .start = MX2x_PWM_BASE_ADDR,
443 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
444 .flags = IORESOURCE_MEM,
445 }, {
446 .start = MX2x_INT_PWM,
447 .end = MX2x_INT_PWM,
448 .flags = IORESOURCE_IRQ,
449 }
450 };
451
452 struct platform_device mxc_pwm_device = {
453 .name = "mxc_pwm",
454 .id = 0,
455 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
456 .resource = mxc_pwm_resources,
457 };
458
459 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
460 static struct resource mxc_sdhc_resources ## n[] = { \
461 { \
462 .start = baseaddr, \
463 .end = baseaddr + SZ_4K - 1, \
464 .flags = IORESOURCE_MEM, \
465 }, { \
466 .start = irq, \
467 .end = irq, \
468 .flags = IORESOURCE_IRQ, \
469 }, { \
470 .start = dmareq, \
471 .end = dmareq, \
472 .flags = IORESOURCE_DMA, \
473 }, \
474 }; \
475 \
476 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
477 \
478 struct platform_device mxc_sdhc_device ## n = { \
479 .name = "mxc-mmc", \
480 .id = n, \
481 .dev = { \
482 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
483 .coherent_dma_mask = DMA_BIT_MASK(32), \
484 }, \
485 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
486 .resource = mxc_sdhc_resources ## n, \
487 }
488
489 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
490 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
491
492 #ifdef CONFIG_MACH_MX27
493 static struct resource otg_resources[] = {
494 {
495 .start = MX27_USBOTG_BASE_ADDR,
496 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
497 .flags = IORESOURCE_MEM,
498 }, {
499 .start = MX27_INT_USB3,
500 .end = MX27_INT_USB3,
501 .flags = IORESOURCE_IRQ,
502 },
503 };
504
505 static u64 otg_dmamask = DMA_BIT_MASK(32);
506
507 /* OTG gadget device */
508 struct platform_device mxc_otg_udc_device = {
509 .name = "fsl-usb2-udc",
510 .id = -1,
511 .dev = {
512 .dma_mask = &otg_dmamask,
513 .coherent_dma_mask = DMA_BIT_MASK(32),
514 },
515 .resource = otg_resources,
516 .num_resources = ARRAY_SIZE(otg_resources),
517 };
518
519 /* OTG host */
520 struct platform_device mxc_otg_host = {
521 .name = "mxc-ehci",
522 .id = 0,
523 .dev = {
524 .coherent_dma_mask = DMA_BIT_MASK(32),
525 .dma_mask = &otg_dmamask,
526 },
527 .resource = otg_resources,
528 .num_resources = ARRAY_SIZE(otg_resources),
529 };
530
531 /* USB host 1 */
532
533 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
534
535 static struct resource mxc_usbh1_resources[] = {
536 {
537 .start = MX27_USBOTG_BASE_ADDR + 0x200,
538 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
539 .flags = IORESOURCE_MEM,
540 }, {
541 .start = MX27_INT_USB1,
542 .end = MX27_INT_USB1,
543 .flags = IORESOURCE_IRQ,
544 },
545 };
546
547 struct platform_device mxc_usbh1 = {
548 .name = "mxc-ehci",
549 .id = 1,
550 .dev = {
551 .coherent_dma_mask = DMA_BIT_MASK(32),
552 .dma_mask = &usbh1_dmamask,
553 },
554 .resource = mxc_usbh1_resources,
555 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
556 };
557
558 /* USB host 2 */
559 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
560
561 static struct resource mxc_usbh2_resources[] = {
562 {
563 .start = MX27_USBOTG_BASE_ADDR + 0x400,
564 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
565 .flags = IORESOURCE_MEM,
566 }, {
567 .start = MX27_INT_USB2,
568 .end = MX27_INT_USB2,
569 .flags = IORESOURCE_IRQ,
570 },
571 };
572
573 struct platform_device mxc_usbh2 = {
574 .name = "mxc-ehci",
575 .id = 2,
576 .dev = {
577 .coherent_dma_mask = DMA_BIT_MASK(32),
578 .dma_mask = &usbh2_dmamask,
579 },
580 .resource = mxc_usbh2_resources,
581 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
582 };
583 #endif
584
585 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
586 { \
587 .name = _name, \
588 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
589 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
590 .flags = IORESOURCE_DMA, \
591 }
592
593 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
594 static struct resource imx_ssi_resources ## n[] = { \
595 { \
596 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
597 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
598 .flags = IORESOURCE_MEM, \
599 }, { \
600 .start = MX2x_INT_SSI1, \
601 .end = MX2x_INT_SSI1, \
602 .flags = IORESOURCE_IRQ, \
603 }, \
604 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
605 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
606 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
607 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
608 }; \
609 \
610 struct platform_device imx_ssi_device ## n = { \
611 .name = "imx-ssi", \
612 .id = n, \
613 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
614 .resource = imx_ssi_resources ## n, \
615 }
616
617 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
618 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
619
620 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq) \
621 static struct resource imx2x_uart_resources ## n[] = { \
622 { \
623 .start = baseaddr, \
624 .end = baseaddr + 0xb5, \
625 .flags = IORESOURCE_MEM, \
626 }, { \
627 .start = irq, \
628 .end = irq, \
629 .flags = IORESOURCE_IRQ, \
630 }, \
631 }; \
632 \
633 struct platform_device imx2x_uart_device ## n = { \
634 .name = "imx-uart", \
635 .id = n, \
636 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
637 .resource = imx2x_uart_resources ## n, \
638 }
639
640 DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
641 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
642 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
643 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
644
645 #ifdef CONFIG_MACH_MX27
646 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
647 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
648 #endif
649
650 /* GPIO port description */
651 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
652 { \
653 .chip.label = "gpio-" #n, \
654 .irq = _irq, \
655 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
656 n * 0x100), \
657 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
658 }
659
660 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
661 { \
662 .chip.label = "gpio-" #n, \
663 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
664 n * 0x100), \
665 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
666 }
667
668 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
669 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
670 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
671 DEFINE_MXC_GPIO_PORT(SOC, 1), \
672 DEFINE_MXC_GPIO_PORT(SOC, 2), \
673 DEFINE_MXC_GPIO_PORT(SOC, 3), \
674 DEFINE_MXC_GPIO_PORT(SOC, 4), \
675 DEFINE_MXC_GPIO_PORT(SOC, 5), \
676 }
677
678 #ifdef CONFIG_MACH_MX21
679 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
680
681 int __init imx21_register_gpios(void)
682 {
683 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
684 }
685 #endif
686
687 #ifdef CONFIG_MACH_MX27
688 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
689
690 int __init imx27_register_gpios(void)
691 {
692 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
693 }
694 #endif
695
696 #ifdef CONFIG_MACH_MX21
697 static struct resource mx21_usbhc_resources[] = {
698 {
699 .start = MX21_USBOTG_BASE_ADDR,
700 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
701 .flags = IORESOURCE_MEM,
702 },
703 {
704 .start = MX21_INT_USBHOST,
705 .end = MX21_INT_USBHOST,
706 .flags = IORESOURCE_IRQ,
707 },
708 };
709
710 struct platform_device mx21_usbhc_device = {
711 .name = "imx21-hcd",
712 .id = 0,
713 .dev = {
714 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
715 .coherent_dma_mask = DMA_BIT_MASK(32),
716 },
717 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
718 .resource = mx21_usbhc_resources,
719 };
720 #endif
721 #endif
Linux kernel - Deliverables
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