2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
34 #include <linux/dma-mapping.h>
36 #include <mach/irqs.h>
37 #include <mach/hardware.h>
38 #include <mach/common.h>
44 * SPI master controller
46 * - i.MX1: 2 channel (slighly different register setting)
50 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
51 static struct resource mxc_spi_resources ## n[] = { \
54 .end = baseaddr + SZ_4K - 1, \
55 .flags = IORESOURCE_MEM, \
59 .flags = IORESOURCE_IRQ, \
63 struct platform_device mxc_spi_device ## n = { \
66 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
67 .resource = mxc_spi_resources ## n, \
70 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR
, MX2x_INT_CSPI1
);
71 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR
, MX2x_INT_CSPI2
);
73 #ifdef CONFIG_MACH_MX27
74 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR
, MX27_INT_CSPI3
);
78 * General Purpose Timer
82 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
83 static struct resource timer ## n ##_resources[] = { \
86 .end = baseaddr + SZ_4K - 1, \
87 .flags = IORESOURCE_MEM, \
91 .flags = IORESOURCE_IRQ, \
95 struct platform_device mxc_gpt ## n = { \
98 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
99 .resource = timer ## n ## _resources, \
102 /* We use gpt1 as system timer, so do not add a device for this one */
103 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR
, MX2x_INT_GPT2
);
104 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR
, MX2x_INT_GPT3
);
106 #ifdef CONFIG_MACH_MX27
107 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR
, MX27_INT_GPT4
);
108 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR
, MX27_INT_GPT5
);
109 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR
, MX27_INT_GPT6
);
112 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
113 static struct resource mxc_wdt_resources
[] = {
115 .start
= MX2x_WDOG_BASE_ADDR
,
116 .end
= MX2x_WDOG_BASE_ADDR
+ SZ_4K
- 1,
117 .flags
= IORESOURCE_MEM
,
121 struct platform_device mxc_wdt
= {
124 .num_resources
= ARRAY_SIZE(mxc_wdt_resources
),
125 .resource
= mxc_wdt_resources
,
128 static struct resource mxc_w1_master_resources
[] = {
130 .start
= MX2x_OWIRE_BASE_ADDR
,
131 .end
= MX2x_OWIRE_BASE_ADDR
+ SZ_4K
- 1,
132 .flags
= IORESOURCE_MEM
,
136 struct platform_device mxc_w1_master_device
= {
139 .num_resources
= ARRAY_SIZE(mxc_w1_master_resources
),
140 .resource
= mxc_w1_master_resources
,
143 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
144 static struct resource pfx ## _nand_resources[] = { \
147 .end = baseaddr + SZ_4K - 1, \
148 .flags = IORESOURCE_MEM, \
152 .flags = IORESOURCE_IRQ, \
156 struct platform_device pfx ## _nand_device = { \
157 .name = "mxc_nand", \
159 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
160 .resource = pfx ## _nand_resources, \
163 #ifdef CONFIG_MACH_MX21
164 DEFINE_MXC_NAND_DEVICE(imx21
, MX21_NFC_BASE_ADDR
, MX21_INT_NANDFC
);
167 #ifdef CONFIG_MACH_MX27
168 DEFINE_MXC_NAND_DEVICE(imx27
, MX27_NFC_BASE_ADDR
, MX27_INT_NANDFC
);
173 * - i.MX1: the basic controller
174 * - i.MX21: to be checked
175 * - i.MX27: like i.MX1, with slightly variations
177 static struct resource mxc_fb
[] = {
179 .start
= MX2x_LCDC_BASE_ADDR
,
180 .end
= MX2x_LCDC_BASE_ADDR
+ SZ_4K
- 1,
181 .flags
= IORESOURCE_MEM
,
183 .start
= MX2x_INT_LCDC
,
184 .end
= MX2x_INT_LCDC
,
185 .flags
= IORESOURCE_IRQ
,
190 struct platform_device mxc_fb_device
= {
193 .num_resources
= ARRAY_SIZE(mxc_fb
),
196 .coherent_dma_mask
= DMA_BIT_MASK(32),
200 #ifdef CONFIG_MACH_MX27
201 static struct resource mxc_fec_resources
[] = {
203 .start
= MX27_FEC_BASE_ADDR
,
204 .end
= MX27_FEC_BASE_ADDR
+ SZ_4K
- 1,
205 .flags
= IORESOURCE_MEM
,
207 .start
= MX27_INT_FEC
,
209 .flags
= IORESOURCE_IRQ
,
213 struct platform_device mxc_fec_device
= {
216 .num_resources
= ARRAY_SIZE(mxc_fec_resources
),
217 .resource
= mxc_fec_resources
,
221 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
222 static struct resource mxc_i2c_resources ## n[] = { \
225 .end = baseaddr + SZ_4K - 1, \
226 .flags = IORESOURCE_MEM, \
230 .flags = IORESOURCE_IRQ, \
234 struct platform_device mxc_i2c_device ## n = { \
237 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
238 .resource = mxc_i2c_resources ## n, \
241 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR
, MX2x_INT_I2C
);
243 #ifdef CONFIG_MACH_MX27
244 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR
, MX27_INT_I2C2
);
247 static struct resource mxc_pwm_resources
[] = {
249 .start
= MX2x_PWM_BASE_ADDR
,
250 .end
= MX2x_PWM_BASE_ADDR
+ SZ_4K
- 1,
251 .flags
= IORESOURCE_MEM
,
253 .start
= MX2x_INT_PWM
,
255 .flags
= IORESOURCE_IRQ
,
259 struct platform_device mxc_pwm_device
= {
262 .num_resources
= ARRAY_SIZE(mxc_pwm_resources
),
263 .resource
= mxc_pwm_resources
,
266 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
267 static struct resource mxc_sdhc_resources ## n[] = { \
270 .end = baseaddr + SZ_4K - 1, \
271 .flags = IORESOURCE_MEM, \
275 .flags = IORESOURCE_IRQ, \
279 .flags = IORESOURCE_DMA, \
283 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
285 struct platform_device mxc_sdhc_device ## n = { \
289 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
290 .coherent_dma_mask = DMA_BIT_MASK(32), \
292 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
293 .resource = mxc_sdhc_resources ## n, \
296 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR
, MX2x_INT_SDHC1
, MX2x_DMA_REQ_SDHC1
);
297 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR
, MX2x_INT_SDHC2
, MX2x_DMA_REQ_SDHC2
);
299 #ifdef CONFIG_MACH_MX27
300 static struct resource otg_resources
[] = {
302 .start
= MX27_USBOTG_BASE_ADDR
,
303 .end
= MX27_USBOTG_BASE_ADDR
+ 0x1ff,
304 .flags
= IORESOURCE_MEM
,
306 .start
= MX27_INT_USB3
,
307 .end
= MX27_INT_USB3
,
308 .flags
= IORESOURCE_IRQ
,
312 static u64 otg_dmamask
= DMA_BIT_MASK(32);
314 /* OTG gadget device */
315 struct platform_device mxc_otg_udc_device
= {
316 .name
= "fsl-usb2-udc",
319 .dma_mask
= &otg_dmamask
,
320 .coherent_dma_mask
= DMA_BIT_MASK(32),
322 .resource
= otg_resources
,
323 .num_resources
= ARRAY_SIZE(otg_resources
),
327 struct platform_device mxc_otg_host
= {
331 .coherent_dma_mask
= DMA_BIT_MASK(32),
332 .dma_mask
= &otg_dmamask
,
334 .resource
= otg_resources
,
335 .num_resources
= ARRAY_SIZE(otg_resources
),
340 static u64 usbh1_dmamask
= DMA_BIT_MASK(32);
342 static struct resource mxc_usbh1_resources
[] = {
344 .start
= MX27_USBOTG_BASE_ADDR
+ 0x200,
345 .end
= MX27_USBOTG_BASE_ADDR
+ 0x3ff,
346 .flags
= IORESOURCE_MEM
,
348 .start
= MX27_INT_USB1
,
349 .end
= MX27_INT_USB1
,
350 .flags
= IORESOURCE_IRQ
,
354 struct platform_device mxc_usbh1
= {
358 .coherent_dma_mask
= DMA_BIT_MASK(32),
359 .dma_mask
= &usbh1_dmamask
,
361 .resource
= mxc_usbh1_resources
,
362 .num_resources
= ARRAY_SIZE(mxc_usbh1_resources
),
366 static u64 usbh2_dmamask
= DMA_BIT_MASK(32);
368 static struct resource mxc_usbh2_resources
[] = {
370 .start
= MX27_USBOTG_BASE_ADDR
+ 0x400,
371 .end
= MX27_USBOTG_BASE_ADDR
+ 0x5ff,
372 .flags
= IORESOURCE_MEM
,
374 .start
= MX27_INT_USB2
,
375 .end
= MX27_INT_USB2
,
376 .flags
= IORESOURCE_IRQ
,
380 struct platform_device mxc_usbh2
= {
384 .coherent_dma_mask
= DMA_BIT_MASK(32),
385 .dma_mask
= &usbh2_dmamask
,
387 .resource
= mxc_usbh2_resources
,
388 .num_resources
= ARRAY_SIZE(mxc_usbh2_resources
),
392 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
395 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
396 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
397 .flags = IORESOURCE_DMA, \
400 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
401 static struct resource imx_ssi_resources ## n[] = { \
403 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
404 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
405 .flags = IORESOURCE_MEM, \
407 .start = MX2x_INT_SSI1, \
408 .end = MX2x_INT_SSI1, \
409 .flags = IORESOURCE_IRQ, \
411 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
412 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
413 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
414 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
417 struct platform_device imx_ssi_device ## n = { \
420 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
421 .resource = imx_ssi_resources ## n, \
424 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR
, MX2x_INT_SSI1
);
425 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR
, MX2x_INT_SSI1
);
427 /* GPIO port description */
428 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
430 .chip.label = "gpio-" #n, \
432 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
434 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
437 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
439 .chip.label = "gpio-" #n, \
440 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
442 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
445 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
446 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
447 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
448 DEFINE_MXC_GPIO_PORT(SOC, 1), \
449 DEFINE_MXC_GPIO_PORT(SOC, 2), \
450 DEFINE_MXC_GPIO_PORT(SOC, 3), \
451 DEFINE_MXC_GPIO_PORT(SOC, 4), \
452 DEFINE_MXC_GPIO_PORT(SOC, 5), \
455 #ifdef CONFIG_MACH_MX21
456 DEFINE_MXC_GPIO_PORTS(MX21
, imx21
);
458 int __init
imx21_register_gpios(void)
460 return mxc_gpio_init(imx21_gpio_ports
, ARRAY_SIZE(imx21_gpio_ports
));
464 #ifdef CONFIG_MACH_MX27
465 DEFINE_MXC_GPIO_PORTS(MX27
, imx27
);
467 int __init
imx27_register_gpios(void)
469 return mxc_gpio_init(imx27_gpio_ports
, ARRAY_SIZE(imx27_gpio_ports
));
473 #ifdef CONFIG_MACH_MX21
474 static struct resource mx21_usbhc_resources
[] = {
476 .start
= MX21_USBOTG_BASE_ADDR
,
477 .end
= MX21_USBOTG_BASE_ADDR
+ SZ_8K
- 1,
478 .flags
= IORESOURCE_MEM
,
481 .start
= MX21_INT_USBHOST
,
482 .end
= MX21_INT_USBHOST
,
483 .flags
= IORESOURCE_IRQ
,
487 struct platform_device mx21_usbhc_device
= {
491 .dma_mask
= &mx21_usbhc_device
.dev
.coherent_dma_mask
,
492 .coherent_dma_mask
= DMA_BIT_MASK(32),
494 .num_resources
= ARRAY_SIZE(mx21_usbhc_resources
),
495 .resource
= mx21_usbhc_resources
,