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ARM: imx: fold serial.c into devices.c
[deliverable/linux.git] / arch / arm / mach-imx / devices.c
1 /*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 * MA 02110-1301, USA.
28 */
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/serial.h>
36
37 #include <mach/irqs.h>
38 #include <mach/hardware.h>
39 #include <mach/common.h>
40 #include <mach/mmc.h>
41 #include <mach/imx-uart.h>
42
43 #include "devices.h"
44
45 /*
46 * SPI master controller
47 *
48 * - i.MX1: 2 channel (slighly different register setting)
49 * - i.MX21: 2 channel
50 * - i.MX27: 3 channel
51 */
52 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
53 static struct resource mxc_spi_resources ## n[] = { \
54 { \
55 .start = baseaddr, \
56 .end = baseaddr + SZ_4K - 1, \
57 .flags = IORESOURCE_MEM, \
58 }, { \
59 .start = irq, \
60 .end = irq, \
61 .flags = IORESOURCE_IRQ, \
62 }, \
63 }; \
64 \
65 struct platform_device mxc_spi_device ## n = { \
66 .name = "spi_imx", \
67 .id = n, \
68 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
69 .resource = mxc_spi_resources ## n, \
70 }
71
72 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
73 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
74
75 #ifdef CONFIG_MACH_MX27
76 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
77 #endif
78
79 /*
80 * General Purpose Timer
81 * - i.MX21: 3 timers
82 * - i.MX27: 6 timers
83 */
84 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
85 static struct resource timer ## n ##_resources[] = { \
86 { \
87 .start = baseaddr, \
88 .end = baseaddr + SZ_4K - 1, \
89 .flags = IORESOURCE_MEM, \
90 }, { \
91 .start = irq, \
92 .end = irq, \
93 .flags = IORESOURCE_IRQ, \
94 } \
95 }; \
96 \
97 struct platform_device mxc_gpt ## n = { \
98 .name = "imx_gpt", \
99 .id = n, \
100 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
101 .resource = timer ## n ## _resources, \
102 }
103
104 /* We use gpt1 as system timer, so do not add a device for this one */
105 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
106 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
107
108 #ifdef CONFIG_MACH_MX27
109 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
110 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
111 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
112 #endif
113
114 /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
115 static struct resource mxc_wdt_resources[] = {
116 {
117 .start = MX2x_WDOG_BASE_ADDR,
118 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 };
122
123 struct platform_device mxc_wdt = {
124 .name = "imx2-wdt",
125 .id = 0,
126 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
127 .resource = mxc_wdt_resources,
128 };
129
130 static struct resource mxc_w1_master_resources[] = {
131 {
132 .start = MX2x_OWIRE_BASE_ADDR,
133 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
134 .flags = IORESOURCE_MEM,
135 },
136 };
137
138 struct platform_device mxc_w1_master_device = {
139 .name = "mxc_w1",
140 .id = 0,
141 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
142 .resource = mxc_w1_master_resources,
143 };
144
145 #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
146 static struct resource pfx ## _nand_resources[] = { \
147 { \
148 .start = baseaddr, \
149 .end = baseaddr + SZ_4K - 1, \
150 .flags = IORESOURCE_MEM, \
151 }, { \
152 .start = irq, \
153 .end = irq, \
154 .flags = IORESOURCE_IRQ, \
155 }, \
156 }; \
157 \
158 struct platform_device pfx ## _nand_device = { \
159 .name = "mxc_nand", \
160 .id = 0, \
161 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
162 .resource = pfx ## _nand_resources, \
163 }
164
165 #ifdef CONFIG_MACH_MX21
166 DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
167 #endif
168
169 #ifdef CONFIG_MACH_MX27
170 DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
171 #endif
172
173 /*
174 * lcdc:
175 * - i.MX1: the basic controller
176 * - i.MX21: to be checked
177 * - i.MX27: like i.MX1, with slightly variations
178 */
179 static struct resource mxc_fb[] = {
180 {
181 .start = MX2x_LCDC_BASE_ADDR,
182 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
183 .flags = IORESOURCE_MEM,
184 }, {
185 .start = MX2x_INT_LCDC,
186 .end = MX2x_INT_LCDC,
187 .flags = IORESOURCE_IRQ,
188 }
189 };
190
191 /* mxc lcd driver */
192 struct platform_device mxc_fb_device = {
193 .name = "imx-fb",
194 .id = 0,
195 .num_resources = ARRAY_SIZE(mxc_fb),
196 .resource = mxc_fb,
197 .dev = {
198 .coherent_dma_mask = DMA_BIT_MASK(32),
199 },
200 };
201
202 #ifdef CONFIG_MACH_MX27
203 static struct resource mxc_fec_resources[] = {
204 {
205 .start = MX27_FEC_BASE_ADDR,
206 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
207 .flags = IORESOURCE_MEM,
208 }, {
209 .start = MX27_INT_FEC,
210 .end = MX27_INT_FEC,
211 .flags = IORESOURCE_IRQ,
212 },
213 };
214
215 struct platform_device mxc_fec_device = {
216 .name = "fec",
217 .id = 0,
218 .num_resources = ARRAY_SIZE(mxc_fec_resources),
219 .resource = mxc_fec_resources,
220 };
221 #endif
222
223 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
224 static struct resource mxc_i2c_resources ## n[] = { \
225 { \
226 .start = baseaddr, \
227 .end = baseaddr + SZ_4K - 1, \
228 .flags = IORESOURCE_MEM, \
229 }, { \
230 .start = irq, \
231 .end = irq, \
232 .flags = IORESOURCE_IRQ, \
233 } \
234 }; \
235 \
236 struct platform_device mxc_i2c_device ## n = { \
237 .name = "imx-i2c", \
238 .id = n, \
239 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
240 .resource = mxc_i2c_resources ## n, \
241 }
242
243 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
244
245 #ifdef CONFIG_MACH_MX27
246 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
247 #endif
248
249 static struct resource mxc_pwm_resources[] = {
250 {
251 .start = MX2x_PWM_BASE_ADDR,
252 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
253 .flags = IORESOURCE_MEM,
254 }, {
255 .start = MX2x_INT_PWM,
256 .end = MX2x_INT_PWM,
257 .flags = IORESOURCE_IRQ,
258 }
259 };
260
261 struct platform_device mxc_pwm_device = {
262 .name = "mxc_pwm",
263 .id = 0,
264 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
265 .resource = mxc_pwm_resources,
266 };
267
268 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
269 static struct resource mxc_sdhc_resources ## n[] = { \
270 { \
271 .start = baseaddr, \
272 .end = baseaddr + SZ_4K - 1, \
273 .flags = IORESOURCE_MEM, \
274 }, { \
275 .start = irq, \
276 .end = irq, \
277 .flags = IORESOURCE_IRQ, \
278 }, { \
279 .start = dmareq, \
280 .end = dmareq, \
281 .flags = IORESOURCE_DMA, \
282 }, \
283 }; \
284 \
285 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
286 \
287 struct platform_device mxc_sdhc_device ## n = { \
288 .name = "mxc-mmc", \
289 .id = n, \
290 .dev = { \
291 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
292 .coherent_dma_mask = DMA_BIT_MASK(32), \
293 }, \
294 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
295 .resource = mxc_sdhc_resources ## n, \
296 }
297
298 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
299 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
300
301 #ifdef CONFIG_MACH_MX27
302 static struct resource otg_resources[] = {
303 {
304 .start = MX27_USBOTG_BASE_ADDR,
305 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
306 .flags = IORESOURCE_MEM,
307 }, {
308 .start = MX27_INT_USB3,
309 .end = MX27_INT_USB3,
310 .flags = IORESOURCE_IRQ,
311 },
312 };
313
314 static u64 otg_dmamask = DMA_BIT_MASK(32);
315
316 /* OTG gadget device */
317 struct platform_device mxc_otg_udc_device = {
318 .name = "fsl-usb2-udc",
319 .id = -1,
320 .dev = {
321 .dma_mask = &otg_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 },
324 .resource = otg_resources,
325 .num_resources = ARRAY_SIZE(otg_resources),
326 };
327
328 /* OTG host */
329 struct platform_device mxc_otg_host = {
330 .name = "mxc-ehci",
331 .id = 0,
332 .dev = {
333 .coherent_dma_mask = DMA_BIT_MASK(32),
334 .dma_mask = &otg_dmamask,
335 },
336 .resource = otg_resources,
337 .num_resources = ARRAY_SIZE(otg_resources),
338 };
339
340 /* USB host 1 */
341
342 static u64 usbh1_dmamask = DMA_BIT_MASK(32);
343
344 static struct resource mxc_usbh1_resources[] = {
345 {
346 .start = MX27_USBOTG_BASE_ADDR + 0x200,
347 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
348 .flags = IORESOURCE_MEM,
349 }, {
350 .start = MX27_INT_USB1,
351 .end = MX27_INT_USB1,
352 .flags = IORESOURCE_IRQ,
353 },
354 };
355
356 struct platform_device mxc_usbh1 = {
357 .name = "mxc-ehci",
358 .id = 1,
359 .dev = {
360 .coherent_dma_mask = DMA_BIT_MASK(32),
361 .dma_mask = &usbh1_dmamask,
362 },
363 .resource = mxc_usbh1_resources,
364 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
365 };
366
367 /* USB host 2 */
368 static u64 usbh2_dmamask = DMA_BIT_MASK(32);
369
370 static struct resource mxc_usbh2_resources[] = {
371 {
372 .start = MX27_USBOTG_BASE_ADDR + 0x400,
373 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
374 .flags = IORESOURCE_MEM,
375 }, {
376 .start = MX27_INT_USB2,
377 .end = MX27_INT_USB2,
378 .flags = IORESOURCE_IRQ,
379 },
380 };
381
382 struct platform_device mxc_usbh2 = {
383 .name = "mxc-ehci",
384 .id = 2,
385 .dev = {
386 .coherent_dma_mask = DMA_BIT_MASK(32),
387 .dma_mask = &usbh2_dmamask,
388 },
389 .resource = mxc_usbh2_resources,
390 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
391 };
392 #endif
393
394 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
395 { \
396 .name = _name, \
397 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
398 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
399 .flags = IORESOURCE_DMA, \
400 }
401
402 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
403 static struct resource imx_ssi_resources ## n[] = { \
404 { \
405 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
406 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
407 .flags = IORESOURCE_MEM, \
408 }, { \
409 .start = MX2x_INT_SSI1, \
410 .end = MX2x_INT_SSI1, \
411 .flags = IORESOURCE_IRQ, \
412 }, \
413 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
414 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
415 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
416 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
417 }; \
418 \
419 struct platform_device imx_ssi_device ## n = { \
420 .name = "imx-ssi", \
421 .id = n, \
422 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
423 .resource = imx_ssi_resources ## n, \
424 }
425
426 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
427 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
428
429 #define DEFINE_IMX_UART_DEVICE(n, baseaddr, irq) \
430 static struct resource imx2x_uart_resources ## n[] = { \
431 { \
432 .start = baseaddr, \
433 .end = baseaddr + 0xb5, \
434 .flags = IORESOURCE_MEM, \
435 }, { \
436 .start = irq, \
437 .end = irq, \
438 .flags = IORESOURCE_IRQ, \
439 }, \
440 }; \
441 \
442 struct platform_device mxc_uart_device ## n = { \
443 .name = "imx-uart", \
444 .id = n, \
445 .num_resources = ARRAY_SIZE(imx2x_uart_resources ## n), \
446 .resource = imx2x_uart_resources ## n, \
447 }
448
449 DEFINE_IMX_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
450 DEFINE_IMX_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
451 DEFINE_IMX_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
452 DEFINE_IMX_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
453
454 #ifdef CONFIG_MACH_MX27
455 DEFINE_IMX_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
456 DEFINE_IMX_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
457 #endif
458
459 /* GPIO port description */
460 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
461 { \
462 .chip.label = "gpio-" #n, \
463 .irq = _irq, \
464 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
465 n * 0x100), \
466 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
467 }
468
469 #define DEFINE_MXC_GPIO_PORT(SOC, n) \
470 { \
471 .chip.label = "gpio-" #n, \
472 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
473 n * 0x100), \
474 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
475 }
476
477 #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
478 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
479 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
480 DEFINE_MXC_GPIO_PORT(SOC, 1), \
481 DEFINE_MXC_GPIO_PORT(SOC, 2), \
482 DEFINE_MXC_GPIO_PORT(SOC, 3), \
483 DEFINE_MXC_GPIO_PORT(SOC, 4), \
484 DEFINE_MXC_GPIO_PORT(SOC, 5), \
485 }
486
487 #ifdef CONFIG_MACH_MX21
488 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
489
490 int __init imx21_register_gpios(void)
491 {
492 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
493 }
494 #endif
495
496 #ifdef CONFIG_MACH_MX27
497 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
498
499 int __init imx27_register_gpios(void)
500 {
501 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
502 }
503 #endif
504
505 #ifdef CONFIG_MACH_MX21
506 static struct resource mx21_usbhc_resources[] = {
507 {
508 .start = MX21_USBOTG_BASE_ADDR,
509 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
510 .flags = IORESOURCE_MEM,
511 },
512 {
513 .start = MX21_INT_USBHOST,
514 .end = MX21_INT_USBHOST,
515 .flags = IORESOURCE_IRQ,
516 },
517 };
518
519 struct platform_device mx21_usbhc_device = {
520 .name = "imx21-hcd",
521 .id = 0,
522 .dev = {
523 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
524 .coherent_dma_mask = DMA_BIT_MASK(32),
525 },
526 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
527 .resource = mx21_usbhc_resources,
528 };
529 #endif
Linux kernel - Deliverables
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