arch/arm/mach-imx/dma.c

   1 /*
   2  *  linux/arch/arm/mach-imx/dma.c
   3  *
   4  *  imx DMA registration and IRQ dispatching
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License version 2 as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  2004-03-03 Sascha Hauer <sascha@saschahauer.de>
  11  *             initial version heavily inspired by
  12  *             linux/arch/arm/mach-pxa/dma.c
  13  *
  14  *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
  15  *             Changed to support scatter gather DMA
  16  *             by taking Russell's code from RiscPC
  17  *
  18  *  2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz>
  19  *             Corrected error handling code.
  20  *
  21  */
  22
  23 #undef DEBUG
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/errno.h>
  30
  31 #include <asm/scatterlist.h>
  32 #include <asm/system.h>
  33 #include <asm/irq.h>
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36 #include <mach/imx-dma.h>
  37
  38 struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
  39
  40 /*
  41  * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
  42  * @dma_ch: i.MX DMA channel number
  43  * @lastcount: number of bytes transferred during last transfer
  44  *
  45  * Functions prepares DMA controller for next sg data chunk transfer.
  46  * The @lastcount argument informs function about number of bytes transferred
  47  * during last block. Zero value can be used for @lastcount to setup DMA
  48  * for the first chunk.
  49  */
  50 static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount)
  51 {
  52         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  53         unsigned int nextcount;
  54         unsigned int nextaddr;
  55
  56         if (!imxdma->name) {
  57                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
  58                        __func__, dma_ch);
  59                 return 0;
  60         }
  61
  62         imxdma->resbytes -= lastcount;
  63
  64         if (!imxdma->sg) {
  65                 pr_debug("imxdma%d: no sg data\n", dma_ch);
  66                 return 0;
  67         }
  68
  69         imxdma->sgbc += lastcount;
  70         if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) {
  71                 if ((imxdma->sgcount <= 1) || !imxdma->resbytes) {
  72                         pr_debug("imxdma%d: sg transfer limit reached\n",
  73                                  dma_ch);
  74                         imxdma->sgcount=0;
  75                         imxdma->sg = NULL;
  76                         return 0;
  77                 } else {
  78                         imxdma->sgcount--;
  79                         imxdma->sg++;
  80                         imxdma->sgbc = 0;
  81                 }
  82         }
  83         nextcount = imxdma->sg->length - imxdma->sgbc;
  84         nextaddr = imxdma->sg->dma_address + imxdma->sgbc;
  85
  86         if(imxdma->resbytes < nextcount)
  87                 nextcount = imxdma->resbytes;
  88
  89         if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
  90                 DAR(dma_ch) = nextaddr;
  91         else
  92                 SAR(dma_ch) = nextaddr;
  93
  94         CNTR(dma_ch) = nextcount;
  95         pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n",
  96                  dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch));
  97
  98         return nextcount;
  99 }
 100
 101 /*
 102  * imx_dma_setup_sg_base - scatter-gather DMA emulation
 103  * @dma_ch: i.MX DMA channel number
 104  * @sg: pointer to the scatter-gather list/vector
 105  * @sgcount: scatter-gather list hungs count
 106  *
 107  * Functions sets up i.MX DMA state for emulated scatter-gather transfer
 108  * and sets up channel registers to be ready for the first chunk
 109  */
 110 static int
 111 imx_dma_setup_sg_base(imx_dmach_t dma_ch,
 112                       struct scatterlist *sg, unsigned int sgcount)
 113 {
 114         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 115
 116         imxdma->sg = sg;
 117         imxdma->sgcount = sgcount;
 118         imxdma->sgbc = 0;
 119         return imx_dma_sg_next(dma_ch, 0);
 120 }
 121
 122 /**
 123  * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer
 124  * @dma_ch: i.MX DMA channel number
 125  * @dma_address: the DMA/physical memory address of the linear data block
 126  *              to transfer
 127  * @dma_length: length of the data block in bytes
 128  * @dev_addr: physical device port address
 129  * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
 130  *           or %DMA_MODE_WRITE from memory to the device
 131  *
 132  * The function setups DMA channel source and destination addresses for transfer
 133  * specified by provided parameters. The scatter-gather emulation is disabled,
 134  * because linear data block
 135  * form the physical address range is transferred.
 136  * Return value: if incorrect parameters are provided -%EINVAL.
 137  *              Zero indicates success.
 138  */
 139 int
 140 imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
 141                      unsigned int dma_length, unsigned int dev_addr,
 142                      unsigned int dmamode)
 143 {
 144         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 145
 146         imxdma->sg = NULL;
 147         imxdma->sgcount = 0;
 148         imxdma->dma_mode = dmamode;
 149         imxdma->resbytes = dma_length;
 150
 151         if (!dma_address) {
 152                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
 153                        dma_ch);
 154                 return -EINVAL;
 155         }
 156
 157         if (!dma_length) {
 158                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
 159                        dma_ch);
 160                 return -EINVAL;
 161         }
 162
 163         if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
 164                 pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n",
 165                         dma_ch, (unsigned int)dma_address, dma_length,
 166                         dev_addr);
 167                 SAR(dma_ch) = dev_addr;
 168                 DAR(dma_ch) = (unsigned int)dma_address;
 169         } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
 170                 pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n",
 171                         dma_ch, (unsigned int)dma_address, dma_length,
 172                         dev_addr);
 173                 SAR(dma_ch) = (unsigned int)dma_address;
 174                 DAR(dma_ch) = dev_addr;
 175         } else {
 176                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
 177                        dma_ch);
 178                 return -EINVAL;
 179         }
 180
 181         CNTR(dma_ch) = dma_length;
 182
 183         return 0;
 184 }
 185
 186 /**
 187  * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
 188  * @dma_ch: i.MX DMA channel number
 189  * @sg: pointer to the scatter-gather list/vector
 190  * @sgcount: scatter-gather list hungs count
 191  * @dma_length: total length of the transfer request in bytes
 192  * @dev_addr: physical device port address
 193  * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
 194  *           or %DMA_MODE_WRITE from memory to the device
 195  *
 196  * The function sets up DMA channel state and registers to be ready for transfer
 197  * specified by provided parameters. The scatter-gather emulation is set up
 198  * according to the parameters.
 199  *
 200  * The full preparation of the transfer requires setup of more register
 201  * by the caller before imx_dma_enable() can be called.
 202  *
 203  * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes
 204  *
 205  * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx
 206  *
 207  * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical
 208  * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified
 209  *
 210  * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
 211  *
 212  * The typical setup for %DMA_MODE_WRITE is specified by next options combination
 213  *
 214  * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
 215  *
 216  * Be careful here and do not mistakenly mix source and target device
 217  * port sizes constants, they are really different:
 218  * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
 219  * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
 220  *
 221  * Return value: if incorrect parameters are provided -%EINVAL.
 222  * Zero indicates success.
 223  */
 224 int
 225 imx_dma_setup_sg(imx_dmach_t dma_ch,
 226                  struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
 227                  unsigned int dev_addr, unsigned int dmamode)
 228 {
 229         int res;
 230         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 231
 232         imxdma->sg = NULL;
 233         imxdma->sgcount = 0;
 234         imxdma->dma_mode = dmamode;
 235         imxdma->resbytes = dma_length;
 236
 237         if (!sg || !sgcount) {
 238                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
 239                        dma_ch);
 240                 return -EINVAL;
 241         }
 242
 243         if (!sg->length) {
 244                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
 245                        dma_ch);
 246                 return -EINVAL;
 247         }
 248
 249         if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
 250                 pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n",
 251                         dma_ch, sg, sgcount, dma_length, dev_addr);
 252                 SAR(dma_ch) = dev_addr;
 253         } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
 254                 pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n",
 255                         dma_ch, sg, sgcount, dma_length, dev_addr);
 256                 DAR(dma_ch) = dev_addr;
 257         } else {
 258                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
 259                        dma_ch);
 260                 return -EINVAL;
 261         }
 262
 263         res = imx_dma_setup_sg_base(dma_ch, sg, sgcount);
 264         if (res <= 0) {
 265                 printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch);
 266                 return -EINVAL;
 267         }
 268
 269         return 0;
 270 }
 271
 272 /**
 273  * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers
 274  * @dma_ch: i.MX DMA channel number
 275  * @irq_handler: the pointer to the function called if the transfer
 276  *              ends successfully
 277  * @err_handler: the pointer to the function called if the premature
 278  *              end caused by error occurs
 279  * @data: user specified value to be passed to the handlers
 280  */
 281 int
 282 imx_dma_setup_handlers(imx_dmach_t dma_ch,
 283                        void (*irq_handler) (int, void *),
 284                        void (*err_handler) (int, void *, int),
 285                        void *data)
 286 {
 287         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 288         unsigned long flags;
 289
 290         if (!imxdma->name) {
 291                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 292                        __func__, dma_ch);
 293                 return -ENODEV;
 294         }
 295
 296         local_irq_save(flags);
 297         DISR = (1 << dma_ch);
 298         imxdma->irq_handler = irq_handler;
 299         imxdma->err_handler = err_handler;
 300         imxdma->data = data;
 301         local_irq_restore(flags);
 302         return 0;
 303 }
 304
 305 /**
 306  * imx_dma_enable - function to start i.MX DMA channel operation
 307  * @dma_ch: i.MX DMA channel number
 308  *
 309  * The channel has to be allocated by driver through imx_dma_request()
 310  * or imx_dma_request_by_prio() function.
 311  * The transfer parameters has to be set to the channel registers through
 312  * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
 313  * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to
 314  * be set prior this function call by the channel user.
 315  */
 316 void imx_dma_enable(imx_dmach_t dma_ch)
 317 {
 318         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 319         unsigned long flags;
 320
 321         pr_debug("imxdma%d: imx_dma_enable\n", dma_ch);
 322
 323         if (!imxdma->name) {
 324                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 325                        __func__, dma_ch);
 326                 return;
 327         }
 328
 329         local_irq_save(flags);
 330         DISR = (1 << dma_ch);
 331         DIMR &= ~(1 << dma_ch);
 332         CCR(dma_ch) |= CCR_CEN;
 333         local_irq_restore(flags);
 334 }
 335
 336 /**
 337  * imx_dma_disable - stop, finish i.MX DMA channel operatin
 338  * @dma_ch: i.MX DMA channel number
 339  */
 340 void imx_dma_disable(imx_dmach_t dma_ch)
 341 {
 342         unsigned long flags;
 343
 344         pr_debug("imxdma%d: imx_dma_disable\n", dma_ch);
 345
 346         local_irq_save(flags);
 347         DIMR |= (1 << dma_ch);
 348         CCR(dma_ch) &= ~CCR_CEN;
 349         DISR = (1 << dma_ch);
 350         local_irq_restore(flags);
 351 }
 352
 353 /**
 354  * imx_dma_request - request/allocate specified channel number
 355  * @dma_ch: i.MX DMA channel number
 356  * @name: the driver/caller own non-%NULL identification
 357  */
 358 int imx_dma_request(imx_dmach_t dma_ch, const char *name)
 359 {
 360         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 361         unsigned long flags;
 362
 363         /* basic sanity checks */
 364         if (!name)
 365                 return -EINVAL;
 366
 367         if (dma_ch >= IMX_DMA_CHANNELS) {
 368                 printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
 369                        __func__, dma_ch);
 370                 return -EINVAL;
 371         }
 372
 373         local_irq_save(flags);
 374         if (imxdma->name) {
 375                 local_irq_restore(flags);
 376                 return -ENODEV;
 377         }
 378
 379         imxdma->name = name;
 380         imxdma->irq_handler = NULL;
 381         imxdma->err_handler = NULL;
 382         imxdma->data = NULL;
 383         imxdma->sg = NULL;
 384         local_irq_restore(flags);
 385         return 0;
 386 }
 387
 388 /**
 389  * imx_dma_free - release previously acquired channel
 390  * @dma_ch: i.MX DMA channel number
 391  */
 392 void imx_dma_free(imx_dmach_t dma_ch)
 393 {
 394         unsigned long flags;
 395         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 396
 397         if (!imxdma->name) {
 398                 printk(KERN_CRIT
 399                        "%s: trying to free channel %d which is already freed\n",
 400                        __func__, dma_ch);
 401                 return;
 402         }
 403
 404         local_irq_save(flags);
 405         /* Disable interrupts */
 406         DIMR |= (1 << dma_ch);
 407         CCR(dma_ch) &= ~CCR_CEN;
 408         imxdma->name = NULL;
 409         local_irq_restore(flags);
 410 }
 411
 412 /**
 413  * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
 414  * @name: the driver/caller own non-%NULL identification
 415  * @prio: one of the hardware distinguished priority level:
 416  *        %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
 417  *
 418  * This function tries to find free channel in the specified priority group
 419  * if the priority cannot be achieved it tries to look for free channel
 420  * in the higher and then even lower priority groups.
 421  *
 422  * Return value: If there is no free channel to allocate, -%ENODEV is returned.
 423  *               On successful allocation channel is returned.
 424  */
 425 imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio)
 426 {
 427         int i;
 428         int best;
 429
 430         switch (prio) {
 431         case (DMA_PRIO_HIGH):
 432                 best = 8;
 433                 break;
 434         case (DMA_PRIO_MEDIUM):
 435                 best = 4;
 436                 break;
 437         case (DMA_PRIO_LOW):
 438         default:
 439                 best = 0;
 440                 break;
 441         }
 442
 443         for (i = best; i < IMX_DMA_CHANNELS; i++) {
 444                 if (!imx_dma_request(i, name)) {
 445                         return i;
 446                 }
 447         }
 448
 449         for (i = best - 1; i >= 0; i--) {
 450                 if (!imx_dma_request(i, name)) {
 451                         return i;
 452                 }
 453         }
 454
 455         printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
 456
 457         return -ENODEV;
 458 }
 459
 460 static irqreturn_t dma_err_handler(int irq, void *dev_id)
 461 {
 462         int i, disr = DISR;
 463         struct imx_dma_channel *channel;
 464         unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
 465         int errcode;
 466
 467         DISR = disr & err_mask;
 468         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 469                 if(!(err_mask & (1 << i)))
 470                         continue;
 471                 channel = &imx_dma_channels[i];
 472                 errcode = 0;
 473
 474                 if (DBTOSR & (1 << i)) {
 475                         DBTOSR = (1 << i);
 476                         errcode |= IMX_DMA_ERR_BURST;
 477                 }
 478                 if (DRTOSR & (1 << i)) {
 479                         DRTOSR = (1 << i);
 480                         errcode |= IMX_DMA_ERR_REQUEST;
 481                 }
 482                 if (DSESR & (1 << i)) {
 483                         DSESR = (1 << i);
 484                         errcode |= IMX_DMA_ERR_TRANSFER;
 485                 }
 486                 if (DBOSR & (1 << i)) {
 487                         DBOSR = (1 << i);
 488                         errcode |= IMX_DMA_ERR_BUFFER;
 489                 }
 490
 491                 /*
 492                  * The cleaning of @sg field would be questionable
 493                  * there, because its value can help to compute
 494                  * remaining/transferred bytes count in the handler
 495                  */
 496                 /*imx_dma_channels[i].sg = NULL;*/
 497
 498                 if (channel->name && channel->err_handler) {
 499                         channel->err_handler(i, channel->data, errcode);
 500                         continue;
 501                 }
 502
 503                 imx_dma_channels[i].sg = NULL;
 504
 505                 printk(KERN_WARNING
 506                        "DMA timeout on channel %d (%s) -%s%s%s%s\n",
 507                        i, channel->name,
 508                        errcode&IMX_DMA_ERR_BURST?    " burst":"",
 509                        errcode&IMX_DMA_ERR_REQUEST?  " request":"",
 510                        errcode&IMX_DMA_ERR_TRANSFER? " transfer":"",
 511                        errcode&IMX_DMA_ERR_BUFFER?   " buffer":"");
 512         }
 513         return IRQ_HANDLED;
 514 }
 515
 516 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 517 {
 518         int i, disr = DISR;
 519
 520         pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 521                      disr);
 522
 523         DISR = disr;
 524         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 525                 if (disr & (1 << i)) {
 526                         struct imx_dma_channel *channel = &imx_dma_channels[i];
 527                         if (channel->name) {
 528                                 if (imx_dma_sg_next(i, CNTR(i))) {
 529                                         CCR(i) &= ~CCR_CEN;
 530                                         mb();
 531                                         CCR(i) |= CCR_CEN;
 532                                 } else {
 533                                         if (channel->irq_handler)
 534                                                 channel->irq_handler(i,
 535                                                         channel->data);
 536                                 }
 537                         } else {
 538                                 /*
 539                                  * IRQ for an unregistered DMA channel:
 540                                  * let's clear the interrupts and disable it.
 541                                  */
 542                                 printk(KERN_WARNING
 543                                        "spurious IRQ for DMA channel %d\n", i);
 544                         }
 545                 }
 546         }
 547         return IRQ_HANDLED;
 548 }
 549
 550 static int __init imx_dma_init(void)
 551 {
 552         int ret;
 553         int i;
 554
 555         /* reset DMA module */
 556         DCR = DCR_DRST;
 557
 558         ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
 559         if (ret) {
 560                 printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
 561                 return ret;
 562         }
 563
 564         ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
 565         if (ret) {
 566                 printk(KERN_CRIT "Wow!  Can't register ERRIRQ for DMA\n");
 567                 free_irq(DMA_INT, NULL);
 568         }
 569
 570         /* enable DMA module */
 571         DCR = DCR_DEN;
 572
 573         /* clear all interrupts */
 574         DISR = (1 << IMX_DMA_CHANNELS) - 1;
 575
 576         /* enable interrupts */
 577         DIMR = (1 << IMX_DMA_CHANNELS) - 1;
 578
 579         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 580                 imx_dma_channels[i].sg = NULL;
 581                 imx_dma_channels[i].dma_num = i;
 582         }
 583
 584         return ret;
 585 }
 586
 587 arch_initcall(imx_dma_init);
 588
 589 EXPORT_SYMBOL(imx_dma_setup_single);
 590 EXPORT_SYMBOL(imx_dma_setup_sg);
 591 EXPORT_SYMBOL(imx_dma_setup_handlers);
 592 EXPORT_SYMBOL(imx_dma_enable);
 593 EXPORT_SYMBOL(imx_dma_disable);
 594 EXPORT_SYMBOL(imx_dma_request);
 595 EXPORT_SYMBOL(imx_dma_free);
 596 EXPORT_SYMBOL(imx_dma_request_by_prio);
 597 EXPORT_SYMBOL(imx_dma_channels);