arch/arm/mach-imx/ehci-imx5.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_data/usb-ehci-mxc.h>
  19
  20 #include "ehci.h"
  21 #include "hardware.h"
  22
  23 #define MXC_OTG_OFFSET                  0
  24 #define MXC_H1_OFFSET                   0x200
  25 #define MXC_H2_OFFSET                   0x400
  26
  27 /* USB_CTRL */
  28 #define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
  29 #define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
  30 #define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
  31 #define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
  32 #define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)       /* HOST1 power mask */
  33
  34 /* USB_PHY_CTRL_FUNC */
  35 #define MXC_OTG_PHYCTRL_OC_POL_BIT      (1 << 9)        /* OTG Polarity of Overcurrent */
  36 #define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
  37 #define MXC_H1_OC_POL_BIT               (1 << 6)        /* UH1 Polarity of Overcurrent */
  38 #define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
  39 #define MXC_OTG_PHYCTRL_PWR_POL_BIT     (1 << 3)        /* OTG Power Pin Polarity */
  40
  41 /* USBH2CTRL */
  42 #define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
  43 #define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
  44 #define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
  45
  46 #define MXC_USBCMD_OFFSET               0x140
  47
  48 /* USBCMD */
  49 #define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
  50
  51 int mx51_initialize_usb_hw(int port, unsigned int flags)
  52 {
  53         unsigned int v;
  54         void __iomem *usb_base;
  55         void __iomem *usbotg_base;
  56         void __iomem *usbother_base;
  57         int ret = 0;
  58
  59         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
  60         if (!usb_base) {
  61                 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
  62                 return -ENOMEM;
  63         }
  64
  65         switch (port) {
  66         case 0: /* OTG port */
  67                 usbotg_base = usb_base + MXC_OTG_OFFSET;
  68                 break;
  69         case 1: /* Host 1 port */
  70                 usbotg_base = usb_base + MXC_H1_OFFSET;
  71                 break;
  72         case 2: /* Host 2 port */
  73                 usbotg_base = usb_base + MXC_H2_OFFSET;
  74                 break;
  75         default:
  76                 printk(KERN_ERR"%s no such port %d\n", __func__, port);
  77                 ret = -ENOENT;
  78                 goto error;
  79         }
  80         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
  81
  82         switch (port) {
  83         case 0: /*OTG port */
  84                 if (flags & MXC_EHCI_INTERNAL_PHY) {
  85                         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
  86
  87                         if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  88                                 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
  89                         else
  90                                 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
  91                         if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
  92                                 /* OC/USBPWR is used */
  93                                 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
  94                         } else {
  95                                 /* OC/USBPWR is not used */
  96                                 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
  97                         }
  98                         if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  99                                 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
 100                         else
 101                                 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
 102                         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 103
 104                         v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 105                         if (flags & MXC_EHCI_WAKEUP_ENABLED)
 106                                 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
 107                         else
 108                                 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
 109                         if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 110                                 v &= ~MXC_OTG_UCTRL_OPM_BIT;
 111                         else
 112                                 v |= MXC_OTG_UCTRL_OPM_BIT;
 113                         __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 114                 }
 115                 break;
 116         case 1: /* Host 1 */
 117                 /*Host ULPI */
 118                 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 119                 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
 120                         /* HOST1 wakeup/ULPI intr enable */
 121                         v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
 122                 } else {
 123                         /* HOST1 wakeup/ULPI intr disable */
 124                         v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
 125                 }
 126
 127                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 128                         v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
 129                 else
 130                         v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
 131                 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 132
 133                 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 134                 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
 135                         v |= MXC_H1_OC_POL_BIT;
 136                 else
 137                         v &= ~MXC_H1_OC_POL_BIT;
 138                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 139                         v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
 140                 else
 141                         v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
 142                 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 143
 144                 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
 145                 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
 146                         /* Interrupt Threshold Control:Immediate (no threshold) */
 147                         v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
 148                 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
 149                 break;
 150         case 2: /* Host 2 ULPI */
 151                 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
 152                 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
 153                         /* HOST1 wakeup/ULPI intr enable */
 154                         v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
 155                 } else {
 156                         /* HOST1 wakeup/ULPI intr disable */
 157                         v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
 158                 }
 159
 160                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 161                         v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
 162                 else
 163                         v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
 164                 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
 165                 break;
 166         }
 167
 168 error:
 169         iounmap(usb_base);
 170         return ret;
 171 }
 172