arch/arm/mach-imx/mach-imx6q.c

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clocksource.h>
  17 #include <linux/cpu.h>
  18 #include <linux/delay.h>
  19 #include <linux/export.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/irqchip.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/opp.h>
  29 #include <linux/phy.h>
  30 #include <linux/reboot.h>
  31 #include <linux/regmap.h>
  32 #include <linux/micrel_phy.h>
  33 #include <linux/mfd/syscon.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/system_misc.h>
  38
  39 #include "common.h"
  40 #include "cpuidle.h"
  41 #include "hardware.h"
  42
  43 static u32 chip_revision;
  44
  45 int imx6q_revision(void)
  46 {
  47         return chip_revision;
  48 }
  49
  50 static void __init imx6q_init_revision(void)
  51 {
  52         u32 rev = imx_anatop_get_digprog();
  53
  54         switch (rev & 0xff) {
  55         case 0:
  56                 chip_revision = IMX_CHIP_REVISION_1_0;
  57                 break;
  58         case 1:
  59                 chip_revision = IMX_CHIP_REVISION_1_1;
  60                 break;
  61         case 2:
  62                 chip_revision = IMX_CHIP_REVISION_1_2;
  63                 break;
  64         default:
  65                 chip_revision = IMX_CHIP_REVISION_UNKNOWN;
  66         }
  67
  68         mxc_set_cpu_type(rev >> 16 & 0xff);
  69 }
  70
  71 static void imx6q_restart(enum reboot_mode mode, const char *cmd)
  72 {
  73         struct device_node *np;
  74         void __iomem *wdog_base;
  75
  76         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  77         wdog_base = of_iomap(np, 0);
  78         if (!wdog_base)
  79                 goto soft;
  80
  81         imx_src_prepare_restart();
  82
  83         /* enable wdog */
  84         writew_relaxed(1 << 2, wdog_base);
  85         /* write twice to ensure the request will not get ignored */
  86         writew_relaxed(1 << 2, wdog_base);
  87
  88         /* wait for reset to assert ... */
  89         mdelay(500);
  90
  91         pr_err("Watchdog reset failed to assert reset\n");
  92
  93         /* delay to allow the serial port to show the message */
  94         mdelay(50);
  95
  96 soft:
  97         /* we'll take a jump through zero as a poor second */
  98         soft_restart(0);
  99 }
 100
 101 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 102 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 103 {
 104         if (IS_BUILTIN(CONFIG_PHYLIB)) {
 105                 /* min rx data delay */
 106                 phy_write(phydev, 0x0b, 0x8105);
 107                 phy_write(phydev, 0x0c, 0x0000);
 108
 109                 /* max rx/tx clock delay, min rx/tx control delay */
 110                 phy_write(phydev, 0x0b, 0x8104);
 111                 phy_write(phydev, 0x0c, 0xf0f0);
 112                 phy_write(phydev, 0x0b, 0x104);
 113         }
 114
 115         return 0;
 116 }
 117
 118 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
 119 {
 120         phy_write(dev, 0x0d, device);
 121         phy_write(dev, 0x0e, reg);
 122         phy_write(dev, 0x0d, (1 << 14) | device);
 123         phy_write(dev, 0x0e, val);
 124 }
 125
 126 static int ksz9031rn_phy_fixup(struct phy_device *dev)
 127 {
 128         /*
 129          * min rx data delay, max rx/tx clock delay,
 130          * min rx/tx control delay
 131          */
 132         mmd_write_reg(dev, 2, 4, 0);
 133         mmd_write_reg(dev, 2, 5, 0);
 134         mmd_write_reg(dev, 2, 8, 0x003ff);
 135
 136         return 0;
 137 }
 138
 139 static int ar8031_phy_fixup(struct phy_device *dev)
 140 {
 141         u16 val;
 142
 143         /* To enable AR8031 output a 125MHz clk from CLK_25M */
 144         phy_write(dev, 0xd, 0x7);
 145         phy_write(dev, 0xe, 0x8016);
 146         phy_write(dev, 0xd, 0x4007);
 147
 148         val = phy_read(dev, 0xe);
 149         val &= 0xffe3;
 150         val |= 0x18;
 151         phy_write(dev, 0xe, val);
 152
 153         /* introduce tx clock delay */
 154         phy_write(dev, 0x1d, 0x5);
 155         val = phy_read(dev, 0x1e);
 156         val |= 0x0100;
 157         phy_write(dev, 0x1e, val);
 158
 159         return 0;
 160 }
 161
 162 static void __init imx6q_sabrelite_cko1_setup(void)
 163 {
 164         struct clk *cko1_sel, *ahb, *cko1;
 165         unsigned long rate;
 166
 167         cko1_sel = clk_get_sys(NULL, "cko1_sel");
 168         ahb = clk_get_sys(NULL, "ahb");
 169         cko1 = clk_get_sys(NULL, "cko1");
 170         if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
 171                 pr_err("cko1 setup failed!\n");
 172                 goto put_clk;
 173         }
 174         clk_set_parent(cko1_sel, ahb);
 175         rate = clk_round_rate(cko1, 16000000);
 176         clk_set_rate(cko1, rate);
 177 put_clk:
 178         if (!IS_ERR(cko1_sel))
 179                 clk_put(cko1_sel);
 180         if (!IS_ERR(ahb))
 181                 clk_put(ahb);
 182         if (!IS_ERR(cko1))
 183                 clk_put(cko1);
 184 }
 185
 186 #define PHY_ID_AR8031   0x004dd074
 187
 188 static void __init imx6q_enet_phy_init(void)
 189 {
 190         if (IS_BUILTIN(CONFIG_PHYLIB)) {
 191                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 192                                 ksz9021rn_phy_fixup);
 193                 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
 194                                 ksz9031rn_phy_fixup);
 195                 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
 196                                 ar8031_phy_fixup);
 197         }
 198 }
 199
 200 static void __init imx6q_sabresd_cko1_setup(void)
 201 {
 202         struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
 203         unsigned long rate;
 204
 205         cko1_sel = clk_get_sys(NULL, "cko1_sel");
 206         pll4 = clk_get_sys(NULL, "pll4_audio");
 207         pll4_post = clk_get_sys(NULL, "pll4_post_div");
 208         cko1 = clk_get_sys(NULL, "cko1");
 209         if (IS_ERR(cko1_sel) || IS_ERR(pll4)
 210                         || IS_ERR(pll4_post) || IS_ERR(cko1)) {
 211                 pr_err("cko1 setup failed!\n");
 212                 goto put_clk;
 213         }
 214         /*
 215          * Setting pll4 at 768MHz (24MHz * 32)
 216          * So its child clock can get 24MHz easily
 217          */
 218         clk_set_rate(pll4, 768000000);
 219
 220         clk_set_parent(cko1_sel, pll4_post);
 221         rate = clk_round_rate(cko1, 24000000);
 222         clk_set_rate(cko1, rate);
 223 put_clk:
 224         if (!IS_ERR(cko1_sel))
 225                 clk_put(cko1_sel);
 226         if (!IS_ERR(pll4_post))
 227                 clk_put(pll4_post);
 228         if (!IS_ERR(pll4))
 229                 clk_put(pll4);
 230         if (!IS_ERR(cko1))
 231                 clk_put(cko1);
 232 }
 233
 234 static void __init imx6q_sabresd_init(void)
 235 {
 236         imx6q_sabresd_cko1_setup();
 237 }
 238
 239 static void __init imx6q_1588_init(void)
 240 {
 241         struct regmap *gpr;
 242
 243         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 244         if (!IS_ERR(gpr))
 245                 regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
 246         else
 247                 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
 248
 249 }
 250 static void __init imx6q_usb_init(void)
 251 {
 252         imx_anatop_usb_chrg_detect_disable();
 253 }
 254
 255 static void __init imx6q_init_machine(void)
 256 {
 257         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 258                 imx6q_sabrelite_cko1_setup();
 259         else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
 260                         of_machine_is_compatible("fsl,imx6dl-sabresd"))
 261                 imx6q_sabresd_init();
 262
 263         imx6q_enet_phy_init();
 264
 265         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 266
 267         imx_anatop_init();
 268         imx6q_pm_init();
 269         imx6q_usb_init();
 270         imx6q_1588_init();
 271 }
 272
 273 #define OCOTP_CFG3                      0x440
 274 #define OCOTP_CFG3_SPEED_SHIFT          16
 275 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 276
 277 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
 278 {
 279         struct device_node *np;
 280         void __iomem *base;
 281         u32 val;
 282
 283         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 284         if (!np) {
 285                 pr_warn("failed to find ocotp node\n");
 286                 return;
 287         }
 288
 289         base = of_iomap(np, 0);
 290         if (!base) {
 291                 pr_warn("failed to map ocotp\n");
 292                 goto put_node;
 293         }
 294
 295         val = readl_relaxed(base + OCOTP_CFG3);
 296         val >>= OCOTP_CFG3_SPEED_SHIFT;
 297         if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
 298                 if (opp_disable(cpu_dev, 1200000000))
 299                         pr_warn("failed to disable 1.2 GHz OPP\n");
 300
 301 put_node:
 302         of_node_put(np);
 303 }
 304
 305 static void __init imx6q_opp_init(struct device *cpu_dev)
 306 {
 307         struct device_node *np;
 308
 309         np = of_find_node_by_path("/cpus/cpu@0");
 310         if (!np) {
 311                 pr_warn("failed to find cpu0 node\n");
 312                 return;
 313         }
 314
 315         cpu_dev->of_node = np;
 316         if (of_init_opp_table(cpu_dev)) {
 317                 pr_warn("failed to init OPP table\n");
 318                 goto put_node;
 319         }
 320
 321         imx6q_opp_check_1p2ghz(cpu_dev);
 322
 323 put_node:
 324         of_node_put(np);
 325 }
 326
 327 static struct platform_device imx6q_cpufreq_pdev = {
 328         .name = "imx6q-cpufreq",
 329 };
 330
 331 static void __init imx6q_init_late(void)
 332 {
 333         /*
 334          * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
 335          * to run cpuidle on them.
 336          */
 337         if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
 338                 imx6q_cpuidle_init();
 339
 340         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
 341                 imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
 342                 platform_device_register(&imx6q_cpufreq_pdev);
 343         }
 344 }
 345
 346 static void __init imx6q_map_io(void)
 347 {
 348         debug_ll_io_init();
 349         imx_scu_map_io();
 350 }
 351
 352 #ifdef CONFIG_CACHE_L2X0
 353 static void __init imx6q_init_l2cache(void)
 354 {
 355         void __iomem *l2x0_base;
 356         struct device_node *np;
 357         unsigned int val;
 358
 359         np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
 360         if (!np)
 361                 goto out;
 362
 363         l2x0_base = of_iomap(np, 0);
 364         if (!l2x0_base) {
 365                 of_node_put(np);
 366                 goto out;
 367         }
 368
 369         /* Configure the L2 PREFETCH and POWER registers */
 370         val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
 371         val |= 0x70800000;
 372         writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
 373         val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
 374         writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
 375
 376         iounmap(l2x0_base);
 377         of_node_put(np);
 378
 379 out:
 380         l2x0_of_init(0, ~0UL);
 381 }
 382 #else
 383 static inline void imx6q_init_l2cache(void) {}
 384 #endif
 385
 386 static void __init imx6q_init_irq(void)
 387 {
 388         imx6q_init_revision();
 389         imx6q_init_l2cache();
 390         imx_src_init();
 391         imx_gpc_init();
 392         irqchip_init();
 393 }
 394
 395 static void __init imx6q_timer_init(void)
 396 {
 397         of_clk_init(NULL);
 398         clocksource_of_init();
 399         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
 400                               imx6q_revision());
 401 }
 402
 403 static const char *imx6q_dt_compat[] __initdata = {
 404         "fsl,imx6dl",
 405         "fsl,imx6q",
 406         NULL,
 407 };
 408
 409 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
 410         .smp            = smp_ops(imx_smp_ops),
 411         .map_io         = imx6q_map_io,
 412         .init_irq       = imx6q_init_irq,
 413         .init_time      = imx6q_timer_init,
 414         .init_machine   = imx6q_init_machine,
 415         .init_late      = imx6q_init_late,
 416         .dt_compat      = imx6q_dt_compat,
 417         .restart        = imx6q_restart,
 418 MACHINE_END