2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/serial_8250.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
25 #include <asm/mach-types.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/time.h>
28 #include <asm/memory.h>
29 #include <asm/mach/map.h>
30 #include <mach/common.h>
31 #include <mach/iomux-mx3.h>
33 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
34 #include <linux/mfd/wm8350/audio.h>
35 #include <linux/mfd/wm8350/core.h>
36 #include <linux/mfd/wm8350/pmic.h>
39 #include "devices-imx31.h"
41 /* Base address of PBC controller */
42 #define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
44 /* PBC Board interrupt status register */
45 #define PBC_INTSTATUS 0x000016
47 /* PBC Board interrupt current status register */
48 #define PBC_INTCURR_STATUS 0x000018
50 /* PBC Interrupt mask register set address */
51 #define PBC_INTMASK_SET 0x00001A
53 /* PBC Interrupt mask register clear address */
54 #define PBC_INTMASK_CLEAR 0x00001C
57 #define PBC_SC16C652_UARTA 0x010000
60 #define PBC_SC16C652_UARTB 0x010010
62 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
63 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
64 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
66 #define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START
67 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
69 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
70 #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
72 #define MXC_MAX_EXP_IO_LINES 16
75 #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
76 #define CS4_CS8900_MMIO_START 0x20000
79 * The serial port definition structure.
81 static struct plat_serial8250_port serial_platform_data
[] = {
83 .membase
= (void *)(PBC_BASE_ADDRESS
+ PBC_SC16C652_UARTA
),
84 .mapbase
= (unsigned long)(MX31_CS4_BASE_ADDR
+ PBC_SC16C652_UARTA
),
85 .irq
= EXPIO_INT_XUART_INTA
,
89 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_AUTO_IRQ
,
91 .membase
= (void *)(PBC_BASE_ADDRESS
+ PBC_SC16C652_UARTB
),
92 .mapbase
= (unsigned long)(MX31_CS4_BASE_ADDR
+ PBC_SC16C652_UARTB
),
93 .irq
= EXPIO_INT_XUART_INTB
,
97 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_AUTO_IRQ
,
102 static struct platform_device serial_device
= {
103 .name
= "serial8250",
106 .platform_data
= serial_platform_data
,
110 static const struct resource mx31ads_cs8900_resources
[] __initconst
= {
111 DEFINE_RES_MEM(MX31_CS4_BASE_ADDR
+ CS4_CS8900_MMIO_START
, SZ_64K
),
112 DEFINE_RES_IRQ(EXPIO_INT_ENET_INT
),
115 static const struct platform_device_info mx31ads_cs8900_devinfo __initconst
= {
118 .res
= mx31ads_cs8900_resources
,
119 .num_res
= ARRAY_SIZE(mx31ads_cs8900_resources
),
122 static int __init
mxc_init_extuart(void)
124 return platform_device_register(&serial_device
);
127 static void __init
mxc_init_ext_ethernet(void)
129 platform_device_register_full(
130 (struct platform_device_info
*)&mx31ads_cs8900_devinfo
);
133 static const struct imxuart_platform_data uart_pdata __initconst
= {
134 .flags
= IMXUART_HAVE_RTSCTS
,
137 static unsigned int uart_pins
[] = {
144 static inline void mxc_init_imx_uart(void)
146 mxc_iomux_setup_multiple_pins(uart_pins
, ARRAY_SIZE(uart_pins
), "uart-0");
147 imx31_add_imx_uart0(&uart_pdata
);
150 static void mx31ads_expio_irq_handler(u32 irq
, struct irq_desc
*desc
)
156 imr_val
= __raw_readw(PBC_INTMASK_SET_REG
);
157 int_valid
= __raw_readw(PBC_INTSTATUS_REG
) & imr_val
;
159 expio_irq
= MXC_EXP_IO_BASE
;
160 for (; int_valid
!= 0; int_valid
>>= 1, expio_irq
++) {
161 if ((int_valid
& 1) == 0)
164 generic_handle_irq(expio_irq
);
169 * Disable an expio pin's interrupt by setting the bit in the imr.
170 * @param d an expio virtual irq description
172 static void expio_mask_irq(struct irq_data
*d
)
174 u32 expio
= MXC_IRQ_TO_EXPIO(d
->irq
);
175 /* mask the interrupt */
176 __raw_writew(1 << expio
, PBC_INTMASK_CLEAR_REG
);
177 __raw_readw(PBC_INTMASK_CLEAR_REG
);
181 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
182 * @param d an expio virtual irq description
184 static void expio_ack_irq(struct irq_data
*d
)
186 u32 expio
= MXC_IRQ_TO_EXPIO(d
->irq
);
187 /* clear the interrupt status */
188 __raw_writew(1 << expio
, PBC_INTSTATUS_REG
);
192 * Enable a expio pin's interrupt by clearing the bit in the imr.
193 * @param d an expio virtual irq description
195 static void expio_unmask_irq(struct irq_data
*d
)
197 u32 expio
= MXC_IRQ_TO_EXPIO(d
->irq
);
198 /* unmask the interrupt */
199 __raw_writew(1 << expio
, PBC_INTMASK_SET_REG
);
202 static struct irq_chip expio_irq_chip
= {
203 .name
= "EXPIO(CPLD)",
204 .irq_ack
= expio_ack_irq
,
205 .irq_mask
= expio_mask_irq
,
206 .irq_unmask
= expio_unmask_irq
,
209 static void __init
mx31ads_init_expio(void)
213 printk(KERN_INFO
"MX31ADS EXPIO(CPLD) hardware\n");
216 * Configure INT line as GPIO input
218 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4
, IOMUX_CONFIG_GPIO
), "expio");
220 /* disable the interrupt and clear the status */
221 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG
);
222 __raw_writew(0xFFFF, PBC_INTSTATUS_REG
);
223 for (i
= MXC_EXP_IO_BASE
; i
< (MXC_EXP_IO_BASE
+ MXC_MAX_EXP_IO_LINES
);
225 irq_set_chip_and_handler(i
, &expio_irq_chip
, handle_level_irq
);
226 set_irq_flags(i
, IRQF_VALID
);
228 irq
= gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4
));
229 irq_set_irq_type(irq
, IRQ_TYPE_LEVEL_HIGH
);
230 irq_set_chained_handler(irq
, mx31ads_expio_irq_handler
);
233 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
234 /* This section defines setup for the Wolfson Microelectronics
235 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
236 * regulator definitions may be shared with them, but for now they can
237 * only be used with this board so would generate warnings about
238 * unused statics and some of the configuration is specific to this
243 static struct regulator_consumer_supply sw1a_consumers
[] = {
249 static struct regulator_init_data sw1a_data
= {
254 .valid_ops_mask
= REGULATOR_CHANGE_VOLTAGE
|
255 REGULATOR_CHANGE_MODE
,
256 .valid_modes_mask
= REGULATOR_MODE_NORMAL
|
260 .mode
= REGULATOR_MODE_NORMAL
,
263 .initial_state
= PM_SUSPEND_MEM
,
267 .num_consumer_supplies
= ARRAY_SIZE(sw1a_consumers
),
268 .consumer_supplies
= sw1a_consumers
,
271 /* System IO - High */
272 static struct regulator_init_data viohi_data
= {
279 .mode
= REGULATOR_MODE_NORMAL
,
282 .initial_state
= PM_SUSPEND_MEM
,
288 /* System IO - Low */
289 static struct regulator_init_data violo_data
= {
296 .mode
= REGULATOR_MODE_NORMAL
,
299 .initial_state
= PM_SUSPEND_MEM
,
306 static struct regulator_init_data sw2a_data
= {
311 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
314 .mode
= REGULATOR_MODE_NORMAL
,
318 .mode
= REGULATOR_MODE_NORMAL
,
323 .initial_state
= PM_SUSPEND_MEM
,
327 static struct regulator_init_data ldo1_data
= {
329 .name
= "VCAM/VMMC1/VMMC2",
332 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
333 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
338 static struct regulator_consumer_supply ldo2_consumers
[] = {
339 { .supply
= "AVDD", .dev_name
= "1-001a" },
340 { .supply
= "HPVDD", .dev_name
= "1-001a" },
344 static struct regulator_init_data ldo2_data
= {
346 .name
= "VESIM/VSIM/AVDD",
349 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
350 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
353 .num_consumer_supplies
= ARRAY_SIZE(ldo2_consumers
),
354 .consumer_supplies
= ldo2_consumers
,
358 static struct regulator_init_data vdig_data
= {
363 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
371 static struct regulator_init_data ldo4_data
= {
373 .name
= "VRF1/CVDD_2.775",
376 .valid_modes_mask
= REGULATOR_MODE_NORMAL
,
383 static struct wm8350_led_platform_data wm8350_led_data
= {
384 .name
= "wm8350:white",
385 .default_trigger
= "heartbeat",
389 static struct wm8350_audio_platform_data imx32ads_wm8350_setup
= {
390 .vmid_discharge_msecs
= 1000,
392 .cap_discharge_msecs
= 700,
393 .vmid_charge_msecs
= 700,
394 .vmid_s_curve
= WM8350_S_CURVE_SLOW
,
395 .dis_out4
= WM8350_DISCHARGE_SLOW
,
396 .dis_out3
= WM8350_DISCHARGE_SLOW
,
397 .dis_out2
= WM8350_DISCHARGE_SLOW
,
398 .dis_out1
= WM8350_DISCHARGE_SLOW
,
399 .vroi_out4
= WM8350_TIE_OFF_500R
,
400 .vroi_out3
= WM8350_TIE_OFF_500R
,
401 .vroi_out2
= WM8350_TIE_OFF_500R
,
402 .vroi_out1
= WM8350_TIE_OFF_500R
,
404 .codec_current_on
= WM8350_CODEC_ISEL_1_0
,
405 .codec_current_standby
= WM8350_CODEC_ISEL_0_5
,
406 .codec_current_charge
= WM8350_CODEC_ISEL_1_5
,
409 static int mx31_wm8350_init(struct wm8350
*wm8350
)
411 wm8350_gpio_config(wm8350
, 0, WM8350_GPIO_DIR_IN
,
412 WM8350_GPIO0_PWR_ON_IN
, WM8350_GPIO_ACTIVE_LOW
,
413 WM8350_GPIO_PULL_UP
, WM8350_GPIO_INVERT_OFF
,
414 WM8350_GPIO_DEBOUNCE_ON
);
416 wm8350_gpio_config(wm8350
, 3, WM8350_GPIO_DIR_IN
,
417 WM8350_GPIO3_PWR_OFF_IN
, WM8350_GPIO_ACTIVE_HIGH
,
418 WM8350_GPIO_PULL_DOWN
, WM8350_GPIO_INVERT_OFF
,
419 WM8350_GPIO_DEBOUNCE_ON
);
421 wm8350_gpio_config(wm8350
, 4, WM8350_GPIO_DIR_IN
,
422 WM8350_GPIO4_MR_IN
, WM8350_GPIO_ACTIVE_HIGH
,
423 WM8350_GPIO_PULL_DOWN
, WM8350_GPIO_INVERT_OFF
,
424 WM8350_GPIO_DEBOUNCE_OFF
);
426 wm8350_gpio_config(wm8350
, 7, WM8350_GPIO_DIR_IN
,
427 WM8350_GPIO7_HIBERNATE_IN
, WM8350_GPIO_ACTIVE_HIGH
,
428 WM8350_GPIO_PULL_DOWN
, WM8350_GPIO_INVERT_OFF
,
429 WM8350_GPIO_DEBOUNCE_OFF
);
431 wm8350_gpio_config(wm8350
, 6, WM8350_GPIO_DIR_OUT
,
432 WM8350_GPIO6_SDOUT_OUT
, WM8350_GPIO_ACTIVE_HIGH
,
433 WM8350_GPIO_PULL_NONE
, WM8350_GPIO_INVERT_OFF
,
434 WM8350_GPIO_DEBOUNCE_OFF
);
436 wm8350_gpio_config(wm8350
, 8, WM8350_GPIO_DIR_OUT
,
437 WM8350_GPIO8_VCC_FAULT_OUT
, WM8350_GPIO_ACTIVE_LOW
,
438 WM8350_GPIO_PULL_NONE
, WM8350_GPIO_INVERT_OFF
,
439 WM8350_GPIO_DEBOUNCE_OFF
);
441 wm8350_gpio_config(wm8350
, 9, WM8350_GPIO_DIR_OUT
,
442 WM8350_GPIO9_BATT_FAULT_OUT
, WM8350_GPIO_ACTIVE_LOW
,
443 WM8350_GPIO_PULL_NONE
, WM8350_GPIO_INVERT_OFF
,
444 WM8350_GPIO_DEBOUNCE_OFF
);
446 wm8350_register_regulator(wm8350
, WM8350_DCDC_1
, &sw1a_data
);
447 wm8350_register_regulator(wm8350
, WM8350_DCDC_3
, &viohi_data
);
448 wm8350_register_regulator(wm8350
, WM8350_DCDC_4
, &violo_data
);
449 wm8350_register_regulator(wm8350
, WM8350_DCDC_6
, &sw2a_data
);
450 wm8350_register_regulator(wm8350
, WM8350_LDO_1
, &ldo1_data
);
451 wm8350_register_regulator(wm8350
, WM8350_LDO_2
, &ldo2_data
);
452 wm8350_register_regulator(wm8350
, WM8350_LDO_3
, &vdig_data
);
453 wm8350_register_regulator(wm8350
, WM8350_LDO_4
, &ldo4_data
);
456 wm8350_dcdc_set_slot(wm8350
, WM8350_DCDC_5
, 1, 1,
457 WM8350_DC5_ERRACT_SHUTDOWN_CONV
);
458 wm8350_isink_set_flash(wm8350
, WM8350_ISINK_A
,
459 WM8350_ISINK_FLASH_DISABLE
,
460 WM8350_ISINK_FLASH_TRIG_BIT
,
461 WM8350_ISINK_FLASH_DUR_32MS
,
462 WM8350_ISINK_FLASH_ON_INSTANT
,
463 WM8350_ISINK_FLASH_OFF_INSTANT
,
464 WM8350_ISINK_FLASH_MODE_EN
);
465 wm8350_dcdc25_set_mode(wm8350
, WM8350_DCDC_5
,
466 WM8350_ISINK_MODE_BOOST
,
467 WM8350_ISINK_ILIM_NORMAL
,
469 WM8350_DC5_FBSRC_ISINKA
);
470 wm8350_register_led(wm8350
, 0, WM8350_DCDC_5
, WM8350_ISINK_A
,
473 wm8350
->codec
.platform_data
= &imx32ads_wm8350_setup
;
475 regulator_has_full_constraints();
480 static struct wm8350_platform_data __initdata mx31_wm8350_pdata
= {
481 .init
= mx31_wm8350_init
,
482 .irq_base
= MXC_BOARD_IRQ_START
+ MXC_MAX_EXP_IO_LINES
,
486 static struct i2c_board_info __initdata mx31ads_i2c1_devices
[] = {
487 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
489 I2C_BOARD_INFO("wm8350", 0x1a),
490 .platform_data
= &mx31_wm8350_pdata
,
491 /* irq number is run-time assigned */
496 static void __init
mxc_init_i2c(void)
498 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
499 mx31ads_i2c1_devices
[0].irq
=
500 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3
));
502 i2c_register_board_info(1, mx31ads_i2c1_devices
,
503 ARRAY_SIZE(mx31ads_i2c1_devices
));
505 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI
, IOMUX_CONFIG_ALT1
));
506 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO
, IOMUX_CONFIG_ALT1
));
508 imx31_add_imx_i2c1(NULL
);
511 static unsigned int ssi_pins
[] = {
514 MX31_PIN_SRXD5__SRXD5
,
515 MX31_PIN_STXD5__STXD5
,
518 static void __init
mxc_init_audio(void)
520 imx31_add_imx_ssi(0, NULL
);
521 mxc_iomux_setup_multiple_pins(ssi_pins
, ARRAY_SIZE(ssi_pins
), "ssi");
525 * Static mappings, starting from the CS4 start address up to the start address
528 static struct map_desc mx31ads_io_desc
[] __initdata
= {
530 .virtual = MX31_CS4_BASE_ADDR_VIRT
,
531 .pfn
= __phys_to_pfn(MX31_CS4_BASE_ADDR
),
532 .length
= CS4_CS8900_MMIO_START
,
537 static void __init
mx31ads_map_io(void)
540 iotable_init(mx31ads_io_desc
, ARRAY_SIZE(mx31ads_io_desc
));
543 static void __init
mx31ads_init_irq(void)
546 mx31ads_init_expio();
549 static void __init
mx31ads_init(void)
557 mxc_init_ext_ethernet();
560 static void __init
mx31ads_timer_init(void)
562 mx31_clocks_init(26000000);
565 static struct sys_timer mx31ads_timer
= {
566 .init
= mx31ads_timer_init
,
569 MACHINE_START(MX31ADS
, "Freescale MX31ADS")
570 /* Maintainer: Freescale Semiconductor, Inc. */
571 .atag_offset
= 0x100,
572 .map_io
= mx31ads_map_io
,
573 .init_early
= imx31_init_early
,
574 .init_irq
= mx31ads_init_irq
,
575 .handle_irq
= imx31_handle_irq
,
576 .timer
= &mx31ads_timer
,
577 .init_machine
= mx31ads_init
,
578 .restart
= mxc_restart
,