arch/arm/mach-imx/mach-qong.c

   1 /*
   2  *  Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/memory.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/mtd/physmap.h>
  21 #include <linux/mtd/nand.h>
  22 #include <linux/gpio.h>
  23
  24 #include <mach/hardware.h>
  25 #include <mach/irqs.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/time.h>
  29 #include <asm/mach/map.h>
  30 #include <mach/common.h>
  31 #include <asm/page.h>
  32 #include <asm/setup.h>
  33 #include <mach/iomux-mx3.h>
  34
  35 #include "devices-imx31.h"
  36
  37 /* FPGA defines */
  38 #define QONG_FPGA_VERSION(major, minor, rev)    \
  39         (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
  40
  41 #define QONG_FPGA_BASEADDR              MX31_CS1_BASE_ADDR
  42 #define QONG_FPGA_PERIPH_SIZE           (1 << 24)
  43
  44 #define QONG_FPGA_CTRL_BASEADDR         QONG_FPGA_BASEADDR
  45 #define QONG_FPGA_CTRL_SIZE             0x10
  46 /* FPGA control registers */
  47 #define QONG_FPGA_CTRL_VERSION          0x00
  48
  49 #define QONG_DNET_ID            1
  50 #define QONG_DNET_BASEADDR      \
  51         (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
  52 #define QONG_DNET_SIZE          0x00001000
  53
  54 static const struct imxuart_platform_data uart_pdata __initconst = {
  55         .flags = IMXUART_HAVE_RTSCTS,
  56 };
  57
  58 static int uart_pins[] = {
  59         MX31_PIN_CTS1__CTS1,
  60         MX31_PIN_RTS1__RTS1,
  61         MX31_PIN_TXD1__TXD1,
  62         MX31_PIN_RXD1__RXD1
  63 };
  64
  65 static inline void __init mxc_init_imx_uart(void)
  66 {
  67         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
  68                         "uart-0");
  69         imx31_add_imx_uart0(&uart_pdata);
  70 }
  71
  72 static struct resource dnet_resources[] = {
  73         {
  74                 .name   = "dnet-memory",
  75                 .start  = QONG_DNET_BASEADDR,
  76                 .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
  77                 .flags  = IORESOURCE_MEM,
  78         }, {
  79                 /* irq number is run-time assigned */
  80                 .flags  = IORESOURCE_IRQ,
  81         },
  82 };
  83
  84 static struct platform_device dnet_device = {
  85         .name                   = "dnet",
  86         .id                     = -1,
  87         .num_resources          = ARRAY_SIZE(dnet_resources),
  88         .resource               = dnet_resources,
  89 };
  90
  91 static int __init qong_init_dnet(void)
  92 {
  93         int ret;
  94
  95         dnet_resources[1].start =
  96                 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
  97         dnet_resources[1].end =
  98                 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
  99         ret = platform_device_register(&dnet_device);
 100         return ret;
 101 }
 102
 103 /* MTD NOR flash */
 104
 105 static struct physmap_flash_data qong_flash_data = {
 106         .width = 2,
 107 };
 108
 109 static struct resource qong_flash_resource = {
 110         .start = MX31_CS0_BASE_ADDR,
 111         .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
 112         .flags = IORESOURCE_MEM,
 113 };
 114
 115 static struct platform_device qong_nor_mtd_device = {
 116         .name = "physmap-flash",
 117         .id = 0,
 118         .dev = {
 119                 .platform_data = &qong_flash_data,
 120                 },
 121         .resource = &qong_flash_resource,
 122         .num_resources = 1,
 123 };
 124
 125 static void qong_init_nor_mtd(void)
 126 {
 127         (void)platform_device_register(&qong_nor_mtd_device);
 128 }
 129
 130 /*
 131  * Hardware specific access to control-lines
 132  */
 133 static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 134 {
 135         struct nand_chip *nand_chip = mtd->priv;
 136
 137         if (cmd == NAND_CMD_NONE)
 138                 return;
 139
 140         if (ctrl & NAND_CLE)
 141                 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
 142         else
 143                 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
 144 }
 145
 146 /*
 147  * Read the Device Ready pin.
 148  */
 149 static int qong_nand_device_ready(struct mtd_info *mtd)
 150 {
 151         return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
 152 }
 153
 154 static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
 155 {
 156         if (chip >= 0)
 157                 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
 158         else
 159                 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
 160 }
 161
 162 static struct platform_nand_data qong_nand_data = {
 163         .chip = {
 164                 .nr_chips               = 1,
 165                 .chip_delay             = 20,
 166                 .options                = 0,
 167         },
 168         .ctrl = {
 169                 .cmd_ctrl               = qong_nand_cmd_ctrl,
 170                 .dev_ready              = qong_nand_device_ready,
 171                 .select_chip            = qong_nand_select_chip,
 172         }
 173 };
 174
 175 static struct resource qong_nand_resource = {
 176         .start          = MX31_CS3_BASE_ADDR,
 177         .end            = MX31_CS3_BASE_ADDR + SZ_32M - 1,
 178         .flags          = IORESOURCE_MEM,
 179 };
 180
 181 static struct platform_device qong_nand_device = {
 182         .name           = "gen_nand",
 183         .id             = -1,
 184         .dev            = {
 185                 .platform_data = &qong_nand_data,
 186         },
 187         .num_resources  = 1,
 188         .resource       = &qong_nand_resource,
 189 };
 190
 191 static void __init qong_init_nand_mtd(void)
 192 {
 193         /* init CS */
 194         __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
 195         __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
 196         __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
 197
 198         mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
 199
 200         /* enable pin */
 201         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
 202         if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
 203                 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
 204
 205         /* ready/busy pin */
 206         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
 207         if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
 208                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
 209
 210         /* write protect pin */
 211         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
 212         if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
 213                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
 214
 215         platform_device_register(&qong_nand_device);
 216 }
 217
 218 static void __init qong_init_fpga(void)
 219 {
 220         void __iomem *regs;
 221         u32 fpga_ver;
 222
 223         regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
 224         if (!regs) {
 225                 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
 226                                 __func__);
 227                 return;
 228         }
 229
 230         fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
 231         iounmap(regs);
 232         printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
 233                         (fpga_ver & 0xF000) >> 12,
 234                         (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
 235         if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
 236                 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
 237                                 "devices won't be registered!\n");
 238                 return;
 239         }
 240
 241         /* register FPGA-based devices */
 242         qong_init_nand_mtd();
 243         qong_init_dnet();
 244 }
 245
 246 /*
 247  * Board specific initialization.
 248  */
 249 static void __init qong_init(void)
 250 {
 251         imx31_soc_init();
 252
 253         mxc_init_imx_uart();
 254         qong_init_nor_mtd();
 255         qong_init_fpga();
 256         imx31_add_imx2_wdt(NULL);
 257 }
 258
 259 static void __init qong_timer_init(void)
 260 {
 261         mx31_clocks_init(26000000);
 262 }
 263
 264 static struct sys_timer qong_timer = {
 265         .init   = qong_timer_init,
 266 };
 267
 268 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
 269         /* Maintainer: DENX Software Engineering GmbH */
 270         .atag_offset = 0x100,
 271         .map_io = mx31_map_io,
 272         .init_early = imx31_init_early,
 273         .init_irq = mx31_init_irq,
 274         .handle_irq = imx31_handle_irq,
 275         .timer = &qong_timer,
 276         .init_machine = qong_init,
 277         .restart        = mxc_restart,
 278 MACHINE_END