arch/arm/mach-imx/mm-imx3.c

   1 /*
   2  *  Copyright (C) 1999,2000 Arm Limited
   3  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   4  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   5  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6  *    - add MX31 specific definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/mm.h>
  20 #include <linux/init.h>
  21 #include <linux/err.h>
  22 #include <linux/pinctrl/machine.h>
  23
  24 #include <asm/pgtable.h>
  25 #include <asm/system_misc.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/mach/map.h>
  28
  29 #include <mach/common.h>
  30 #include <mach/devices-common.h>
  31 #include <mach/hardware.h>
  32 #include <mach/iomux-v3.h>
  33 #include <mach/irqs.h>
  34
  35 static void imx3_idle(void)
  36 {
  37         unsigned long reg = 0;
  38
  39         mx3_cpu_lp_set(MX3_WAIT);
  40
  41         __asm__ __volatile__(
  42                 /* disable I and D cache */
  43                 "mrc p15, 0, %0, c1, c0, 0\n"
  44                 "bic %0, %0, #0x00001000\n"
  45                 "bic %0, %0, #0x00000004\n"
  46                 "mcr p15, 0, %0, c1, c0, 0\n"
  47                 /* invalidate I cache */
  48                 "mov %0, #0\n"
  49                 "mcr p15, 0, %0, c7, c5, 0\n"
  50                 /* clear and invalidate D cache */
  51                 "mov %0, #0\n"
  52                 "mcr p15, 0, %0, c7, c14, 0\n"
  53                 /* WFI */
  54                 "mov %0, #0\n"
  55                 "mcr p15, 0, %0, c7, c0, 4\n"
  56                 "nop\n" "nop\n" "nop\n" "nop\n"
  57                 "nop\n" "nop\n" "nop\n"
  58                 /* enable I and D cache */
  59                 "mrc p15, 0, %0, c1, c0, 0\n"
  60                 "orr %0, %0, #0x00001000\n"
  61                 "orr %0, %0, #0x00000004\n"
  62                 "mcr p15, 0, %0, c1, c0, 0\n"
  63                 : "=r" (reg));
  64 }
  65
  66 static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
  67                                          unsigned int mtype, void *caller)
  68 {
  69         if (mtype == MT_DEVICE) {
  70                 /*
  71                  * Access all peripherals below 0x80000000 as nonshared device
  72                  * on mx3, but leave l2cc alone.  Otherwise cache corruptions
  73                  * can occur.
  74                  */
  75                 if (phys_addr < 0x80000000 &&
  76                                 !addr_in_module(phys_addr, MX3x_L2CC))
  77                         mtype = MT_DEVICE_NONSHARED;
  78         }
  79
  80         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
  81 }
  82
  83 void __init imx3_init_l2x0(void)
  84 {
  85         void __iomem *l2x0_base;
  86         void __iomem *clkctl_base;
  87
  88 /*
  89  * First of all, we must repair broken chip settings. There are some
  90  * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
  91  * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
  92  * Workaraound is to setup the correct register setting prior enabling the
  93  * L2 cache. This should not hurt already working CPUs, as they are using the
  94  * same value.
  95  */
  96 #define L2_MEM_VAL 0x10
  97
  98         clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
  99         if (clkctl_base != NULL) {
 100                 writel(0x00000515, clkctl_base + L2_MEM_VAL);
 101                 iounmap(clkctl_base);
 102         } else {
 103                 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
 104         }
 105
 106         l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
 107         if (IS_ERR(l2x0_base)) {
 108                 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
 109                                 PTR_ERR(l2x0_base));
 110                 return;
 111         }
 112
 113         l2x0_init(l2x0_base, 0x00030024, 0x00000000);
 114 }
 115
 116 #ifdef CONFIG_SOC_IMX31
 117 static struct map_desc mx31_io_desc[] __initdata = {
 118         imx_map_entry(MX31, X_MEMC, MT_DEVICE),
 119         imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
 120         imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
 121         imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
 122         imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
 123 };
 124
 125 /*
 126  * This function initializes the memory map. It is called during the
 127  * system startup to create static physical to virtual memory mappings
 128  * for the IO modules.
 129  */
 130 void __init mx31_map_io(void)
 131 {
 132         iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
 133 }
 134
 135 void __init imx31_init_early(void)
 136 {
 137         mxc_set_cpu_type(MXC_CPU_MX31);
 138         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 139         arch_ioremap_caller = imx3_ioremap_caller;
 140         arm_pm_idle = imx3_idle;
 141 }
 142
 143 void __init mx31_init_irq(void)
 144 {
 145         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
 146 }
 147
 148 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
 149         .per_2_per_addr = 1677,
 150 };
 151
 152 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
 153         .ap_2_ap_addr = 423,
 154         .ap_2_bp_addr = 829,
 155         .bp_2_ap_addr = 1029,
 156 };
 157
 158 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
 159         .fw_name = "sdma-imx31-to2.bin",
 160         .script_addrs = &imx31_to2_sdma_script,
 161 };
 162
 163 static const struct resource imx31_audmux_res[] __initconst = {
 164         DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
 165 };
 166
 167 void __init imx31_soc_init(void)
 168 {
 169         int to_version = mx31_revision() >> 4;
 170
 171         imx3_init_l2x0();
 172
 173         mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
 174         mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
 175         mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
 176
 177         if (to_version == 1) {
 178                 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
 179                         strlen(imx31_sdma_pdata.fw_name));
 180                 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
 181         }
 182
 183         imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
 184
 185         imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
 186         imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
 187
 188         platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
 189                                         ARRAY_SIZE(imx31_audmux_res));
 190 }
 191 #endif /* ifdef CONFIG_SOC_IMX31 */
 192
 193 #ifdef CONFIG_SOC_IMX35
 194 static struct map_desc mx35_io_desc[] __initdata = {
 195         imx_map_entry(MX35, X_MEMC, MT_DEVICE),
 196         imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
 197         imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
 198         imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
 199         imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
 200 };
 201
 202 void __init mx35_map_io(void)
 203 {
 204         iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
 205 }
 206
 207 void __init imx35_init_early(void)
 208 {
 209         mxc_set_cpu_type(MXC_CPU_MX35);
 210         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 211         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 212         arm_pm_idle = imx3_idle;
 213         arch_ioremap_caller = imx3_ioremap_caller;
 214 }
 215
 216 void __init mx35_init_irq(void)
 217 {
 218         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
 219 }
 220
 221 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
 222         .ap_2_ap_addr = 642,
 223         .uart_2_mcu_addr = 817,
 224         .mcu_2_app_addr = 747,
 225         .uartsh_2_mcu_addr = 1183,
 226         .per_2_shp_addr = 1033,
 227         .mcu_2_shp_addr = 961,
 228         .ata_2_mcu_addr = 1333,
 229         .mcu_2_ata_addr = 1252,
 230         .app_2_mcu_addr = 683,
 231         .shp_2_per_addr = 1111,
 232         .shp_2_mcu_addr = 892,
 233 };
 234
 235 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
 236         .ap_2_ap_addr = 729,
 237         .uart_2_mcu_addr = 904,
 238         .per_2_app_addr = 1597,
 239         .mcu_2_app_addr = 834,
 240         .uartsh_2_mcu_addr = 1270,
 241         .per_2_shp_addr = 1120,
 242         .mcu_2_shp_addr = 1048,
 243         .ata_2_mcu_addr = 1429,
 244         .mcu_2_ata_addr = 1339,
 245         .app_2_per_addr = 1531,
 246         .app_2_mcu_addr = 770,
 247         .shp_2_per_addr = 1198,
 248         .shp_2_mcu_addr = 979,
 249 };
 250
 251 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
 252         .fw_name = "sdma-imx35-to2.bin",
 253         .script_addrs = &imx35_to2_sdma_script,
 254 };
 255
 256 static const struct resource imx35_audmux_res[] __initconst = {
 257         DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
 258 };
 259
 260 void __init imx35_soc_init(void)
 261 {
 262         int to_version = mx35_revision() >> 4;
 263
 264         imx3_init_l2x0();
 265
 266         /* i.mx35 has the i.mx31 type gpio */
 267         mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
 268         mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
 269         mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 270
 271         pinctrl_provide_dummies();
 272         if (to_version == 1) {
 273                 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
 274                         strlen(imx35_sdma_pdata.fw_name));
 275                 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
 276         }
 277
 278         imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
 279
 280         /* Setup AIPS registers */
 281         imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
 282         imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
 283
 284         /* i.mx35 has the i.mx31 type audmux */
 285         platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
 286                                         ARRAY_SIZE(imx35_audmux_res));
 287 }
 288 #endif /* ifdef CONFIG_SOC_IMX35 */