2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/pinctrl/machine.h>
24 #include <asm/pgtable.h>
25 #include <asm/system_misc.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/mach/map.h>
29 #include <mach/common.h>
30 #include <mach/devices-common.h>
31 #include <mach/hardware.h>
32 #include <mach/iomux-v3.h>
33 #include <mach/irqs.h>
35 #include "crmregs-imx3.h"
37 void __iomem
*mx3_ccm_base
;
39 static void imx3_idle(void)
41 unsigned long reg
= 0;
43 mx3_cpu_lp_set(MX3_WAIT
);
46 /* disable I and D cache */
47 "mrc p15, 0, %0, c1, c0, 0\n"
48 "bic %0, %0, #0x00001000\n"
49 "bic %0, %0, #0x00000004\n"
50 "mcr p15, 0, %0, c1, c0, 0\n"
51 /* invalidate I cache */
53 "mcr p15, 0, %0, c7, c5, 0\n"
54 /* clear and invalidate D cache */
56 "mcr p15, 0, %0, c7, c14, 0\n"
59 "mcr p15, 0, %0, c7, c0, 4\n"
60 "nop\n" "nop\n" "nop\n" "nop\n"
61 "nop\n" "nop\n" "nop\n"
62 /* enable I and D cache */
63 "mrc p15, 0, %0, c1, c0, 0\n"
64 "orr %0, %0, #0x00001000\n"
65 "orr %0, %0, #0x00000004\n"
66 "mcr p15, 0, %0, c1, c0, 0\n"
70 static void __iomem
*imx3_ioremap_caller(unsigned long phys_addr
, size_t size
,
71 unsigned int mtype
, void *caller
)
73 if (mtype
== MT_DEVICE
) {
75 * Access all peripherals below 0x80000000 as nonshared device
76 * on mx3, but leave l2cc alone. Otherwise cache corruptions
79 if (phys_addr
< 0x80000000 &&
80 !addr_in_module(phys_addr
, MX3x_L2CC
))
81 mtype
= MT_DEVICE_NONSHARED
;
84 return __arm_ioremap_caller(phys_addr
, size
, mtype
, caller
);
87 void __init
imx3_init_l2x0(void)
89 void __iomem
*l2x0_base
;
90 void __iomem
*clkctl_base
;
93 * First of all, we must repair broken chip settings. There are some
94 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
95 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
96 * Workaraound is to setup the correct register setting prior enabling the
97 * L2 cache. This should not hurt already working CPUs, as they are using the
100 #define L2_MEM_VAL 0x10
102 clkctl_base
= ioremap(MX35_CLKCTL_BASE_ADDR
, 4096);
103 if (clkctl_base
!= NULL
) {
104 writel(0x00000515, clkctl_base
+ L2_MEM_VAL
);
105 iounmap(clkctl_base
);
107 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
110 l2x0_base
= ioremap(MX3x_L2CC_BASE_ADDR
, 4096);
111 if (IS_ERR(l2x0_base
)) {
112 printk(KERN_ERR
"remapping L2 cache area failed with %ld\n",
117 l2x0_init(l2x0_base
, 0x00030024, 0x00000000);
120 #ifdef CONFIG_SOC_IMX31
121 static struct map_desc mx31_io_desc
[] __initdata
= {
122 imx_map_entry(MX31
, X_MEMC
, MT_DEVICE
),
123 imx_map_entry(MX31
, AVIC
, MT_DEVICE_NONSHARED
),
124 imx_map_entry(MX31
, AIPS1
, MT_DEVICE_NONSHARED
),
125 imx_map_entry(MX31
, AIPS2
, MT_DEVICE_NONSHARED
),
126 imx_map_entry(MX31
, SPBA0
, MT_DEVICE_NONSHARED
),
130 * This function initializes the memory map. It is called during the
131 * system startup to create static physical to virtual memory mappings
132 * for the IO modules.
134 void __init
mx31_map_io(void)
136 iotable_init(mx31_io_desc
, ARRAY_SIZE(mx31_io_desc
));
139 void __init
imx31_init_early(void)
141 mxc_set_cpu_type(MXC_CPU_MX31
);
142 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR
));
143 arch_ioremap_caller
= imx3_ioremap_caller
;
144 arm_pm_idle
= imx3_idle
;
145 mx3_ccm_base
= MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR
);
148 void __init
mx31_init_irq(void)
150 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR
));
153 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata
= {
154 .per_2_per_addr
= 1677,
157 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata
= {
160 .bp_2_ap_addr
= 1029,
163 static struct sdma_platform_data imx31_sdma_pdata __initdata
= {
164 .fw_name
= "sdma-imx31-to2.bin",
165 .script_addrs
= &imx31_to2_sdma_script
,
168 static const struct resource imx31_audmux_res
[] __initconst
= {
169 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR
, SZ_16K
),
172 void __init
imx31_soc_init(void)
174 int to_version
= mx31_revision() >> 4;
178 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR
, SZ_16K
, MX31_INT_GPIO1
, 0);
179 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR
, SZ_16K
, MX31_INT_GPIO2
, 0);
180 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR
, SZ_16K
, MX31_INT_GPIO3
, 0);
182 if (to_version
== 1) {
183 strncpy(imx31_sdma_pdata
.fw_name
, "sdma-imx31-to1.bin",
184 strlen(imx31_sdma_pdata
.fw_name
));
185 imx31_sdma_pdata
.script_addrs
= &imx31_to1_sdma_script
;
188 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR
, MX31_INT_SDMA
, &imx31_sdma_pdata
);
190 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR
));
191 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR
));
193 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res
,
194 ARRAY_SIZE(imx31_audmux_res
));
196 #endif /* ifdef CONFIG_SOC_IMX31 */
198 #ifdef CONFIG_SOC_IMX35
199 static struct map_desc mx35_io_desc
[] __initdata
= {
200 imx_map_entry(MX35
, X_MEMC
, MT_DEVICE
),
201 imx_map_entry(MX35
, AVIC
, MT_DEVICE_NONSHARED
),
202 imx_map_entry(MX35
, AIPS1
, MT_DEVICE_NONSHARED
),
203 imx_map_entry(MX35
, AIPS2
, MT_DEVICE_NONSHARED
),
204 imx_map_entry(MX35
, SPBA0
, MT_DEVICE_NONSHARED
),
207 void __init
mx35_map_io(void)
209 iotable_init(mx35_io_desc
, ARRAY_SIZE(mx35_io_desc
));
212 void __init
imx35_init_early(void)
214 mxc_set_cpu_type(MXC_CPU_MX35
);
215 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR
));
216 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR
));
217 arm_pm_idle
= imx3_idle
;
218 arch_ioremap_caller
= imx3_ioremap_caller
;
219 mx3_ccm_base
= MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR
);
222 void __init
mx35_init_irq(void)
224 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR
));
227 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata
= {
229 .uart_2_mcu_addr
= 817,
230 .mcu_2_app_addr
= 747,
231 .uartsh_2_mcu_addr
= 1183,
232 .per_2_shp_addr
= 1033,
233 .mcu_2_shp_addr
= 961,
234 .ata_2_mcu_addr
= 1333,
235 .mcu_2_ata_addr
= 1252,
236 .app_2_mcu_addr
= 683,
237 .shp_2_per_addr
= 1111,
238 .shp_2_mcu_addr
= 892,
241 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata
= {
243 .uart_2_mcu_addr
= 904,
244 .per_2_app_addr
= 1597,
245 .mcu_2_app_addr
= 834,
246 .uartsh_2_mcu_addr
= 1270,
247 .per_2_shp_addr
= 1120,
248 .mcu_2_shp_addr
= 1048,
249 .ata_2_mcu_addr
= 1429,
250 .mcu_2_ata_addr
= 1339,
251 .app_2_per_addr
= 1531,
252 .app_2_mcu_addr
= 770,
253 .shp_2_per_addr
= 1198,
254 .shp_2_mcu_addr
= 979,
257 static struct sdma_platform_data imx35_sdma_pdata __initdata
= {
258 .fw_name
= "sdma-imx35-to2.bin",
259 .script_addrs
= &imx35_to2_sdma_script
,
262 static const struct resource imx35_audmux_res
[] __initconst
= {
263 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR
, SZ_16K
),
266 void __init
imx35_soc_init(void)
268 int to_version
= mx35_revision() >> 4;
272 /* i.mx35 has the i.mx31 type gpio */
273 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR
, SZ_16K
, MX35_INT_GPIO1
, 0);
274 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR
, SZ_16K
, MX35_INT_GPIO2
, 0);
275 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR
, SZ_16K
, MX35_INT_GPIO3
, 0);
277 pinctrl_provide_dummies();
278 if (to_version
== 1) {
279 strncpy(imx35_sdma_pdata
.fw_name
, "sdma-imx35-to1.bin",
280 strlen(imx35_sdma_pdata
.fw_name
));
281 imx35_sdma_pdata
.script_addrs
= &imx35_to1_sdma_script
;
284 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR
, MX35_INT_SDMA
, &imx35_sdma_pdata
);
286 /* Setup AIPS registers */
287 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR
));
288 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR
));
290 /* i.mx35 has the i.mx31 type audmux */
291 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res
,
292 ARRAY_SIZE(imx35_audmux_res
));
294 #endif /* ifdef CONFIG_SOC_IMX35 */