ARM: imx: include common.h rather than mach/common.h
[deliverable/linux.git] / arch / arm / mach-imx / mm-imx5.c
1 /*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14 #include <linux/mm.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/pinctrl/machine.h>
18
19 #include <asm/mach/map.h>
20
21 #include <mach/hardware.h>
22
23 #include "common.h"
24 #include "devices/devices-common.h"
25 #include "iomux-v3.h"
26
27 /*
28 * Define the MX50 memory map.
29 */
30 static struct map_desc mx50_io_desc[] __initdata = {
31 imx_map_entry(MX50, TZIC, MT_DEVICE),
32 imx_map_entry(MX50, SPBA0, MT_DEVICE),
33 imx_map_entry(MX50, AIPS1, MT_DEVICE),
34 imx_map_entry(MX50, AIPS2, MT_DEVICE),
35 };
36
37 /*
38 * Define the MX51 memory map.
39 */
40 static struct map_desc mx51_io_desc[] __initdata = {
41 imx_map_entry(MX51, TZIC, MT_DEVICE),
42 imx_map_entry(MX51, IRAM, MT_DEVICE),
43 imx_map_entry(MX51, AIPS1, MT_DEVICE),
44 imx_map_entry(MX51, SPBA0, MT_DEVICE),
45 imx_map_entry(MX51, AIPS2, MT_DEVICE),
46 };
47
48 /*
49 * Define the MX53 memory map.
50 */
51 static struct map_desc mx53_io_desc[] __initdata = {
52 imx_map_entry(MX53, TZIC, MT_DEVICE),
53 imx_map_entry(MX53, AIPS1, MT_DEVICE),
54 imx_map_entry(MX53, SPBA0, MT_DEVICE),
55 imx_map_entry(MX53, AIPS2, MT_DEVICE),
56 };
57
58 /*
59 * This function initializes the memory map. It is called during the
60 * system startup to create static physical to virtual memory mappings
61 * for the IO modules.
62 */
63 void __init mx50_map_io(void)
64 {
65 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
66 }
67
68 void __init mx51_map_io(void)
69 {
70 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
71 }
72
73 void __init mx53_map_io(void)
74 {
75 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
76 }
77
78 void __init imx50_init_early(void)
79 {
80 mxc_set_cpu_type(MXC_CPU_MX50);
81 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
83 }
84
85 void __init imx51_init_early(void)
86 {
87 mxc_set_cpu_type(MXC_CPU_MX51);
88 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
89 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
90 }
91
92 void __init imx53_init_early(void)
93 {
94 mxc_set_cpu_type(MXC_CPU_MX53);
95 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
96 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
97 }
98
99 void __init mx50_init_irq(void)
100 {
101 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
102 }
103
104 void __init mx51_init_irq(void)
105 {
106 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
107 }
108
109 void __init mx53_init_irq(void)
110 {
111 tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
112 }
113
114 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
115 .ap_2_ap_addr = 642,
116 .uart_2_mcu_addr = 817,
117 .mcu_2_app_addr = 747,
118 .mcu_2_shp_addr = 961,
119 .ata_2_mcu_addr = 1473,
120 .mcu_2_ata_addr = 1392,
121 .app_2_per_addr = 1033,
122 .app_2_mcu_addr = 683,
123 .shp_2_per_addr = 1251,
124 .shp_2_mcu_addr = 892,
125 };
126
127 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
128 .fw_name = "sdma-imx51.bin",
129 .script_addrs = &imx51_sdma_script,
130 };
131
132 static const struct resource imx50_audmux_res[] __initconst = {
133 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
134 };
135
136 static const struct resource imx51_audmux_res[] __initconst = {
137 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
138 };
139
140 void __init imx50_soc_init(void)
141 {
142 /* i.mx50 has the i.mx35 type gpio */
143 mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
144 mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
145 mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
146 mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
147 mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
148 mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
149
150 /* i.mx50 has the i.mx31 type audmux */
151 platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
152 ARRAY_SIZE(imx50_audmux_res));
153 }
154
155 void __init imx51_soc_init(void)
156 {
157 /* i.mx51 has the i.mx35 type gpio */
158 mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
159 mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
160 mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
161 mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
162
163 pinctrl_provide_dummies();
164
165 /* i.mx51 has the i.mx35 type sdma */
166 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
167
168 /* Setup AIPS registers */
169 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
170 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
171
172 /* i.mx51 has the i.mx31 type audmux */
173 platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
174 ARRAY_SIZE(imx51_audmux_res));
175 }
176
177 void __init imx51_init_late(void)
178 {
179 mx51_neon_fixup();
180 imx51_pm_init();
181 }
182
183 void __init imx53_init_late(void)
184 {
185 imx53_pm_init();
186 }
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