arch/arm/mach-imx/mm-imx5.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License.  You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * Create static mapping between physical to virtual memory.
  12  */
  13
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/hardware.h>
  21 #include <mach/common.h>
  22 #include <mach/devices-common.h>
  23 #include <mach/iomux-v3.h>
  24
  25 static struct clk *gpc_dvfs_clk;
  26
  27 static void imx5_idle(void)
  28 {
  29         /* gpc clock is needed for SRPG */
  30         if (gpc_dvfs_clk == NULL) {
  31                 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
  32                 if (IS_ERR(gpc_dvfs_clk))
  33                         return;
  34         }
  35         clk_enable(gpc_dvfs_clk);
  36         mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
  37         if (tzic_enable_wake() != 0)
  38                 cpu_do_idle();
  39         clk_disable(gpc_dvfs_clk);
  40 }
  41
  42 /*
  43  * Define the MX50 memory map.
  44  */
  45 static struct map_desc mx50_io_desc[] __initdata = {
  46         imx_map_entry(MX50, TZIC, MT_DEVICE),
  47         imx_map_entry(MX50, SPBA0, MT_DEVICE),
  48         imx_map_entry(MX50, AIPS1, MT_DEVICE),
  49         imx_map_entry(MX50, AIPS2, MT_DEVICE),
  50 };
  51
  52 /*
  53  * Define the MX51 memory map.
  54  */
  55 static struct map_desc mx51_io_desc[] __initdata = {
  56         imx_map_entry(MX51, TZIC, MT_DEVICE),
  57         imx_map_entry(MX51, IRAM, MT_DEVICE),
  58         imx_map_entry(MX51, AIPS1, MT_DEVICE),
  59         imx_map_entry(MX51, SPBA0, MT_DEVICE),
  60         imx_map_entry(MX51, AIPS2, MT_DEVICE),
  61 };
  62
  63 /*
  64  * Define the MX53 memory map.
  65  */
  66 static struct map_desc mx53_io_desc[] __initdata = {
  67         imx_map_entry(MX53, TZIC, MT_DEVICE),
  68         imx_map_entry(MX53, AIPS1, MT_DEVICE),
  69         imx_map_entry(MX53, SPBA0, MT_DEVICE),
  70         imx_map_entry(MX53, AIPS2, MT_DEVICE),
  71 };
  72
  73 /*
  74  * This function initializes the memory map. It is called during the
  75  * system startup to create static physical to virtual memory mappings
  76  * for the IO modules.
  77  */
  78 void __init mx50_map_io(void)
  79 {
  80         iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
  81 }
  82
  83 void __init mx51_map_io(void)
  84 {
  85         iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  86 }
  87
  88 void __init mx53_map_io(void)
  89 {
  90         iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  91 }
  92
  93 void __init imx50_init_early(void)
  94 {
  95         mxc_set_cpu_type(MXC_CPU_MX50);
  96         mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
  97         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
  98 }
  99
 100 void __init imx51_init_early(void)
 101 {
 102         mxc_set_cpu_type(MXC_CPU_MX51);
 103         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
 104         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 105         arm_pm_idle = imx5_idle;
 106 }
 107
 108 void __init imx53_init_early(void)
 109 {
 110         mxc_set_cpu_type(MXC_CPU_MX53);
 111         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
 112         mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 113 }
 114
 115 void __init mx50_init_irq(void)
 116 {
 117         tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
 118 }
 119
 120 void __init mx51_init_irq(void)
 121 {
 122         tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
 123 }
 124
 125 void __init mx53_init_irq(void)
 126 {
 127         tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
 128 }
 129
 130 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
 131         .ap_2_ap_addr = 642,
 132         .uart_2_mcu_addr = 817,
 133         .mcu_2_app_addr = 747,
 134         .mcu_2_shp_addr = 961,
 135         .ata_2_mcu_addr = 1473,
 136         .mcu_2_ata_addr = 1392,
 137         .app_2_per_addr = 1033,
 138         .app_2_mcu_addr = 683,
 139         .shp_2_per_addr = 1251,
 140         .shp_2_mcu_addr = 892,
 141 };
 142
 143 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
 144         .fw_name = "sdma-imx51.bin",
 145         .script_addrs = &imx51_sdma_script,
 146 };
 147
 148 static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
 149         .ap_2_ap_addr = 642,
 150         .app_2_mcu_addr = 683,
 151         .mcu_2_app_addr = 747,
 152         .uart_2_mcu_addr = 817,
 153         .shp_2_mcu_addr = 891,
 154         .mcu_2_shp_addr = 960,
 155         .uartsh_2_mcu_addr = 1032,
 156         .spdif_2_mcu_addr = 1100,
 157         .mcu_2_spdif_addr = 1134,
 158         .firi_2_mcu_addr = 1193,
 159         .mcu_2_firi_addr = 1290,
 160 };
 161
 162 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
 163         .fw_name = "sdma-imx53.bin",
 164         .script_addrs = &imx53_sdma_script,
 165 };
 166
 167 static const struct resource imx50_audmux_res[] __initconst = {
 168         DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
 169 };
 170
 171 static const struct resource imx51_audmux_res[] __initconst = {
 172         DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 173 };
 174
 175 static const struct resource imx53_audmux_res[] __initconst = {
 176         DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
 177 };
 178
 179 void __init imx50_soc_init(void)
 180 {
 181         /* i.mx50 has the i.mx31 type gpio */
 182         mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
 183         mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
 184         mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
 185         mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
 186         mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
 187         mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
 188
 189         /* i.mx50 has the i.mx31 type audmux */
 190         platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
 191                                         ARRAY_SIZE(imx50_audmux_res));
 192 }
 193
 194 void __init imx51_soc_init(void)
 195 {
 196         /* i.mx51 has the i.mx31 type gpio */
 197         mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
 198         mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
 199         mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
 200         mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 201
 202         /* i.mx51 has the i.mx35 type sdma */
 203         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
 204         /* i.mx51 has the i.mx31 type audmux */
 205         platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
 206                                         ARRAY_SIZE(imx51_audmux_res));
 207 }
 208
 209 void __init imx53_soc_init(void)
 210 {
 211         /* i.mx53 has the i.mx31 type gpio */
 212         mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
 213         mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
 214         mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
 215         mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
 216         mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
 217         mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
 218         mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
 219
 220         /* i.mx53 has the i.mx35 type sdma */
 221         imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
 222         /* i.mx53 has the i.mx31 type audmux */
 223         platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
 224                                         ARRAY_SIZE(imx53_audmux_res));
 225 }