arch/arm/mach-imx/pm-imx6.c

   1 /*
   2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/genalloc.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/regmap.h>
  24 #include <linux/suspend.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/fncpy.h>
  27 #include <asm/proc-fns.h>
  28 #include <asm/suspend.h>
  29 #include <asm/tlb.h>
  30
  31 #include "common.h"
  32 #include "hardware.h"
  33
  34 #define CCR                             0x0
  35 #define BM_CCR_WB_COUNT                 (0x7 << 16)
  36 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
  37 #define BM_CCR_RBC_EN                   (0x1 << 27)
  38
  39 #define CLPCR                           0x54
  40 #define BP_CLPCR_LPM                    0
  41 #define BM_CLPCR_LPM                    (0x3 << 0)
  42 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
  43 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
  44 #define BM_CLPCR_SBYOS                  (0x1 << 6)
  45 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
  46 #define BM_CLPCR_VSTBY                  (0x1 << 8)
  47 #define BP_CLPCR_STBY_COUNT             9
  48 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
  49 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
  50 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
  51 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
  52 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
  53 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
  54 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
  55 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
  56 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
  57 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
  58 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
  59 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
  60
  61 #define CGPR                            0x64
  62 #define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
  63
  64 #define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
  65 #define MX6_MAX_MMDC_IO_NUM             33
  66
  67 static void __iomem *ccm_base;
  68 static void __iomem *suspend_ocram_base;
  69 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
  70
  71 /*
  72  * suspend ocram space layout:
  73  * ======================== high address ======================
  74  *                              .
  75  *                              .
  76  *                              .
  77  *                              ^
  78  *                              ^
  79  *                              ^
  80  *                      imx6_suspend code
  81  *              PM_INFO structure(imx6_cpu_pm_info)
  82  * ======================== low address =======================
  83  */
  84
  85 struct imx6_pm_base {
  86         phys_addr_t pbase;
  87         void __iomem *vbase;
  88 };
  89
  90 struct imx6_pm_socdata {
  91         u32 cpu_type;
  92         const char *mmdc_compat;
  93         const char *src_compat;
  94         const char *iomuxc_compat;
  95         const char *gpc_compat;
  96         const u32 mmdc_io_num;
  97         const u32 *mmdc_io_offset;
  98 };
  99
 100 static const u32 imx6q_mmdc_io_offset[] __initconst = {
 101         0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
 102         0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
 103         0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 104         0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
 105         0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
 106         0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
 107         0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 108         0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
 109         0x74c,                      /* GPR_ADDS */
 110 };
 111
 112 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
 113         0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
 114         0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
 115         0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 116         0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
 117         0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
 118         0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
 119         0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 120         0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
 121         0x74c,                      /* GPR_ADDS */
 122 };
 123
 124 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
 125         0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
 126         0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
 127         0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 128         0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
 129         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 130 };
 131
 132 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 133         0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
 134         0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
 135         0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 136         0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
 137         0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
 138 };
 139
 140 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 141         .cpu_type = MXC_CPU_IMX6Q,
 142         .mmdc_compat = "fsl,imx6q-mmdc",
 143         .src_compat = "fsl,imx6q-src",
 144         .iomuxc_compat = "fsl,imx6q-iomuxc",
 145         .gpc_compat = "fsl,imx6q-gpc",
 146         .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
 147         .mmdc_io_offset = imx6q_mmdc_io_offset,
 148 };
 149
 150 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 151         .cpu_type = MXC_CPU_IMX6DL,
 152         .mmdc_compat = "fsl,imx6q-mmdc",
 153         .src_compat = "fsl,imx6q-src",
 154         .iomuxc_compat = "fsl,imx6dl-iomuxc",
 155         .gpc_compat = "fsl,imx6q-gpc",
 156         .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
 157         .mmdc_io_offset = imx6dl_mmdc_io_offset,
 158 };
 159
 160 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 161         .cpu_type = MXC_CPU_IMX6SL,
 162         .mmdc_compat = "fsl,imx6sl-mmdc",
 163         .src_compat = "fsl,imx6sl-src",
 164         .iomuxc_compat = "fsl,imx6sl-iomuxc",
 165         .gpc_compat = "fsl,imx6sl-gpc",
 166         .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
 167         .mmdc_io_offset = imx6sl_mmdc_io_offset,
 168 };
 169
 170 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 171         .cpu_type = MXC_CPU_IMX6SX,
 172         .mmdc_compat = "fsl,imx6sx-mmdc",
 173         .src_compat = "fsl,imx6sx-src",
 174         .iomuxc_compat = "fsl,imx6sx-iomuxc",
 175         .gpc_compat = "fsl,imx6sx-gpc",
 176         .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
 177         .mmdc_io_offset = imx6sx_mmdc_io_offset,
 178 };
 179
 180 /*
 181  * This structure is for passing necessary data for low level ocram
 182  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
 183  * definition is changed, the offset definition in
 184  * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
 185  * otherwise, the suspend to ocram function will be broken!
 186  */
 187 struct imx6_cpu_pm_info {
 188         phys_addr_t pbase; /* The physical address of pm_info. */
 189         phys_addr_t resume_addr; /* The physical resume address for asm code */
 190         u32 cpu_type;
 191         u32 pm_info_size; /* Size of pm_info. */
 192         struct imx6_pm_base mmdc_base;
 193         struct imx6_pm_base src_base;
 194         struct imx6_pm_base iomuxc_base;
 195         struct imx6_pm_base ccm_base;
 196         struct imx6_pm_base gpc_base;
 197         struct imx6_pm_base l2_base;
 198         u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
 199         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 200 } __aligned(8);
 201
 202 void imx6q_set_int_mem_clk_lpm(void)
 203 {
 204         u32 val = readl_relaxed(ccm_base + CGPR);
 205
 206         val |= BM_CGPR_INT_MEM_CLK_LPM;
 207         writel_relaxed(val, ccm_base + CGPR);
 208 }
 209
 210 static void imx6q_enable_rbc(bool enable)
 211 {
 212         u32 val;
 213
 214         /*
 215          * need to mask all interrupts in GPC before
 216          * operating RBC configurations
 217          */
 218         imx_gpc_mask_all();
 219
 220         /* configure RBC enable bit */
 221         val = readl_relaxed(ccm_base + CCR);
 222         val &= ~BM_CCR_RBC_EN;
 223         val |= enable ? BM_CCR_RBC_EN : 0;
 224         writel_relaxed(val, ccm_base + CCR);
 225
 226         /* configure RBC count */
 227         val = readl_relaxed(ccm_base + CCR);
 228         val &= ~BM_CCR_RBC_BYPASS_COUNT;
 229         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
 230         writel(val, ccm_base + CCR);
 231
 232         /*
 233          * need to delay at least 2 cycles of CKIL(32K)
 234          * due to hardware design requirement, which is
 235          * ~61us, here we use 65us for safe
 236          */
 237         udelay(65);
 238
 239         /* restore GPC interrupt mask settings */
 240         imx_gpc_restore_all();
 241 }
 242
 243 static void imx6q_enable_wb(bool enable)
 244 {
 245         u32 val;
 246
 247         /* configure well bias enable bit */
 248         val = readl_relaxed(ccm_base + CLPCR);
 249         val &= ~BM_CLPCR_WB_PER_AT_LPM;
 250         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
 251         writel_relaxed(val, ccm_base + CLPCR);
 252
 253         /* configure well bias count */
 254         val = readl_relaxed(ccm_base + CCR);
 255         val &= ~BM_CCR_WB_COUNT;
 256         val |= enable ? BM_CCR_WB_COUNT : 0;
 257         writel_relaxed(val, ccm_base + CCR);
 258 }
 259
 260 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
 261 {
 262         struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
 263         u32 val = readl_relaxed(ccm_base + CLPCR);
 264
 265         val &= ~BM_CLPCR_LPM;
 266         switch (mode) {
 267         case WAIT_CLOCKED:
 268                 break;
 269         case WAIT_UNCLOCKED:
 270                 val |= 0x1 << BP_CLPCR_LPM;
 271                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
 272                 break;
 273         case STOP_POWER_ON:
 274                 val |= 0x2 << BP_CLPCR_LPM;
 275                 break;
 276         case WAIT_UNCLOCKED_POWER_OFF:
 277                 val |= 0x1 << BP_CLPCR_LPM;
 278                 val &= ~BM_CLPCR_VSTBY;
 279                 val &= ~BM_CLPCR_SBYOS;
 280                 break;
 281         case STOP_POWER_OFF:
 282                 val |= 0x2 << BP_CLPCR_LPM;
 283                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
 284                 val |= BM_CLPCR_VSTBY;
 285                 val |= BM_CLPCR_SBYOS;
 286                 if (cpu_is_imx6sl())
 287                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 288                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
 289                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 290                 else
 291                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 292                 break;
 293         default:
 294                 return -EINVAL;
 295         }
 296
 297         /*
 298          * ERR007265: CCM: When improper low-power sequence is used,
 299          * the SoC enters low power mode before the ARM core executes WFI.
 300          *
 301          * Software workaround:
 302          * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
 303          *    by setting IOMUX_GPR1_GINT.
 304          * 2) Software should then unmask IRQ #32 in GPC before setting CCM
 305          *    Low-Power mode.
 306          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
 307          *    is set (set bits 0-1 of CCM_CLPCR).
 308          */
 309         imx_gpc_irq_unmask(iomuxc_irq_data);
 310         writel_relaxed(val, ccm_base + CLPCR);
 311         imx_gpc_irq_mask(iomuxc_irq_data);
 312
 313         return 0;
 314 }
 315
 316 static int imx6q_suspend_finish(unsigned long val)
 317 {
 318         if (!imx6_suspend_in_ocram_fn) {
 319                 cpu_do_idle();
 320         } else {
 321                 /*
 322                  * call low level suspend function in ocram,
 323                  * as we need to float DDR IO.
 324                  */
 325                 local_flush_tlb_all();
 326                 imx6_suspend_in_ocram_fn(suspend_ocram_base);
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int imx6q_pm_enter(suspend_state_t state)
 333 {
 334         switch (state) {
 335         case PM_SUSPEND_MEM:
 336                 imx6q_set_lpm(STOP_POWER_OFF);
 337                 imx6q_enable_wb(true);
 338                 /*
 339                  * For suspend into ocram, asm code already take care of
 340                  * RBC setting, so we do NOT need to do that here.
 341                  */
 342                 if (!imx6_suspend_in_ocram_fn)
 343                         imx6q_enable_rbc(true);
 344                 imx_gpc_pre_suspend();
 345                 imx_anatop_pre_suspend();
 346                 imx_set_cpu_jump(0, v7_cpu_resume);
 347                 /* Zzz ... */
 348                 cpu_suspend(0, imx6q_suspend_finish);
 349                 if (cpu_is_imx6q() || cpu_is_imx6dl())
 350                         imx_smp_prepare();
 351                 imx_anatop_post_resume();
 352                 imx_gpc_post_resume();
 353                 imx6q_enable_rbc(false);
 354                 imx6q_enable_wb(false);
 355                 imx6q_set_lpm(WAIT_CLOCKED);
 356                 break;
 357         default:
 358                 return -EINVAL;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static const struct platform_suspend_ops imx6q_pm_ops = {
 365         .enter = imx6q_pm_enter,
 366         .valid = suspend_valid_only_mem,
 367 };
 368
 369 void __init imx6q_pm_set_ccm_base(void __iomem *base)
 370 {
 371         ccm_base = base;
 372 }
 373
 374 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
 375                                 const char *compat)
 376 {
 377         struct device_node *node;
 378         struct resource res;
 379         int ret = 0;
 380
 381         node = of_find_compatible_node(NULL, NULL, compat);
 382         if (!node) {
 383                 ret = -ENODEV;
 384                 goto out;
 385         }
 386
 387         ret = of_address_to_resource(node, 0, &res);
 388         if (ret)
 389                 goto put_node;
 390
 391         base->pbase = res.start;
 392         base->vbase = ioremap(res.start, resource_size(&res));
 393         if (!base->vbase)
 394                 ret = -ENOMEM;
 395
 396 put_node:
 397         of_node_put(node);
 398 out:
 399         return ret;
 400 }
 401
 402 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
 403 {
 404         phys_addr_t ocram_pbase;
 405         struct device_node *node;
 406         struct platform_device *pdev;
 407         struct imx6_cpu_pm_info *pm_info;
 408         struct gen_pool *ocram_pool;
 409         unsigned long ocram_base;
 410         int i, ret = 0;
 411         const u32 *mmdc_offset_array;
 412
 413         suspend_set_ops(&imx6q_pm_ops);
 414
 415         if (!socdata) {
 416                 pr_warn("%s: invalid argument!\n", __func__);
 417                 return -EINVAL;
 418         }
 419
 420         node = of_find_compatible_node(NULL, NULL, "mmio-sram");
 421         if (!node) {
 422                 pr_warn("%s: failed to find ocram node!\n", __func__);
 423                 return -ENODEV;
 424         }
 425
 426         pdev = of_find_device_by_node(node);
 427         if (!pdev) {
 428                 pr_warn("%s: failed to find ocram device!\n", __func__);
 429                 ret = -ENODEV;
 430                 goto put_node;
 431         }
 432
 433         ocram_pool = dev_get_gen_pool(&pdev->dev);
 434         if (!ocram_pool) {
 435                 pr_warn("%s: ocram pool unavailable!\n", __func__);
 436                 ret = -ENODEV;
 437                 goto put_node;
 438         }
 439
 440         ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
 441         if (!ocram_base) {
 442                 pr_warn("%s: unable to alloc ocram!\n", __func__);
 443                 ret = -ENOMEM;
 444                 goto put_node;
 445         }
 446
 447         ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
 448
 449         suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
 450                 MX6Q_SUSPEND_OCRAM_SIZE, false);
 451
 452         pm_info = suspend_ocram_base;
 453         pm_info->pbase = ocram_pbase;
 454         pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
 455         pm_info->pm_info_size = sizeof(*pm_info);
 456
 457         /*
 458          * ccm physical address is not used by asm code currently,
 459          * so get ccm virtual address directly, as we already have
 460          * it from ccm driver.
 461          */
 462         pm_info->ccm_base.vbase = ccm_base;
 463
 464         ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
 465         if (ret) {
 466                 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
 467                 goto put_node;
 468         }
 469
 470         ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
 471         if (ret) {
 472                 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
 473                 goto src_map_failed;
 474         }
 475
 476         ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
 477         if (ret) {
 478                 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
 479                 goto iomuxc_map_failed;
 480         }
 481
 482         ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
 483         if (ret) {
 484                 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
 485                 goto gpc_map_failed;
 486         }
 487
 488         ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
 489         if (ret) {
 490                 pr_warn("%s: failed to get pl310-cache base %d!\n",
 491                         __func__, ret);
 492                 goto pl310_cache_map_failed;
 493         }
 494
 495         pm_info->cpu_type = socdata->cpu_type;
 496         pm_info->mmdc_io_num = socdata->mmdc_io_num;
 497         mmdc_offset_array = socdata->mmdc_io_offset;
 498
 499         for (i = 0; i < pm_info->mmdc_io_num; i++) {
 500                 pm_info->mmdc_io_val[i][0] =
 501                         mmdc_offset_array[i];
 502                 pm_info->mmdc_io_val[i][1] =
 503                         readl_relaxed(pm_info->iomuxc_base.vbase +
 504                         mmdc_offset_array[i]);
 505         }
 506
 507         imx6_suspend_in_ocram_fn = fncpy(
 508                 suspend_ocram_base + sizeof(*pm_info),
 509                 &imx6_suspend,
 510                 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
 511
 512         goto put_node;
 513
 514 pl310_cache_map_failed:
 515         iounmap(&pm_info->gpc_base.vbase);
 516 gpc_map_failed:
 517         iounmap(&pm_info->iomuxc_base.vbase);
 518 iomuxc_map_failed:
 519         iounmap(&pm_info->src_base.vbase);
 520 src_map_failed:
 521         iounmap(&pm_info->mmdc_base.vbase);
 522 put_node:
 523         of_node_put(node);
 524
 525         return ret;
 526 }
 527
 528 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
 529                                         *socdata)
 530 {
 531         struct regmap *gpr;
 532         int ret;
 533
 534         WARN_ON(!ccm_base);
 535
 536         if (IS_ENABLED(CONFIG_SUSPEND)) {
 537                 ret = imx6q_suspend_init(socdata);
 538                 if (ret)
 539                         pr_warn("%s: No DDR LPM support with suspend %d!\n",
 540                                 __func__, ret);
 541         }
 542
 543         /*
 544          * This is for SW workaround step #1 of ERR007265, see comments
 545          * in imx6q_set_lpm for details of this errata.
 546          * Force IOMUXC irq pending, so that the interrupt to GPC can be
 547          * used to deassert dsm_request signal when the signal gets
 548          * asserted unexpectedly.
 549          */
 550         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 551         if (!IS_ERR(gpr))
 552                 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
 553                                    IMX6Q_GPR1_GINT);
 554 }
 555
 556 void __init imx6q_pm_init(void)
 557 {
 558         imx6_pm_common_init(&imx6q_pm_data);
 559 }
 560
 561 void __init imx6dl_pm_init(void)
 562 {
 563         imx6_pm_common_init(&imx6dl_pm_data);
 564 }
 565
 566 void __init imx6sl_pm_init(void)
 567 {
 568         imx6_pm_common_init(&imx6sl_pm_data);
 569 }
 570
 571 void __init imx6sx_pm_init(void)
 572 {
 573         imx6_pm_common_init(&imx6sx_pm_data);
 574 }