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[deliverable/linux.git] / arch / arm / mach-imx / time.c
1 /*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/err.h>
30 #include <linux/sched_clock.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34
35 #include <asm/mach/time.h>
36
37 #include "common.h"
38 #include "hardware.h"
39
40 /*
41 * There are 4 versions of the timer hardware on Freescale MXC hardware.
42 * - MX1/MXL
43 * - MX21, MX27.
44 * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
45 * - MX6DL, MX6SX, MX6Q(rev1.1+)
46 */
47
48 /* defines common for all i.MX */
49 #define MXC_TCTL 0x00
50 #define MXC_TCTL_TEN (1 << 0) /* Enable module */
51 #define MXC_TPRER 0x04
52
53 /* MX1, MX21, MX27 */
54 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
55 #define MX1_2_TCTL_IRQEN (1 << 4)
56 #define MX1_2_TCTL_FRR (1 << 8)
57 #define MX1_2_TCMP 0x08
58 #define MX1_2_TCN 0x10
59 #define MX1_2_TSTAT 0x14
60
61 /* MX21, MX27 */
62 #define MX2_TSTAT_CAPT (1 << 1)
63 #define MX2_TSTAT_COMP (1 << 0)
64
65 /* MX31, MX35, MX25, MX5, MX6 */
66 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
67 #define V2_TCTL_CLK_IPG (1 << 6)
68 #define V2_TCTL_CLK_PER (2 << 6)
69 #define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
70 #define V2_TCTL_FRR (1 << 9)
71 #define V2_TCTL_24MEN (1 << 10)
72 #define V2_TPRER_PRE24M 12
73 #define V2_IR 0x0c
74 #define V2_TSTAT 0x08
75 #define V2_TSTAT_OF1 (1 << 0)
76 #define V2_TCN 0x24
77 #define V2_TCMP 0x10
78
79 #define V2_TIMER_RATE_OSC_DIV8 3000000
80
81 #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
82 #define timer_is_v2() (!timer_is_v1())
83
84 static struct clock_event_device clockevent_mxc;
85 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
86
87 static void __iomem *timer_base;
88
89 static inline void gpt_irq_disable(void)
90 {
91 unsigned int tmp;
92
93 if (timer_is_v2())
94 __raw_writel(0, timer_base + V2_IR);
95 else {
96 tmp = __raw_readl(timer_base + MXC_TCTL);
97 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
98 }
99 }
100
101 static inline void gpt_irq_enable(void)
102 {
103 if (timer_is_v2())
104 __raw_writel(1<<0, timer_base + V2_IR);
105 else {
106 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
107 timer_base + MXC_TCTL);
108 }
109 }
110
111 static void gpt_irq_acknowledge(void)
112 {
113 if (timer_is_v1()) {
114 if (cpu_is_mx1())
115 __raw_writel(0, timer_base + MX1_2_TSTAT);
116 else
117 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
118 timer_base + MX1_2_TSTAT);
119 } else if (timer_is_v2())
120 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
121 }
122
123 static void __iomem *sched_clock_reg;
124
125 static u64 notrace mxc_read_sched_clock(void)
126 {
127 return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
128 }
129
130 static struct delay_timer imx_delay_timer;
131
132 static unsigned long imx_read_current_timer(void)
133 {
134 return __raw_readl(sched_clock_reg);
135 }
136
137 static int __init mxc_clocksource_init(struct clk *timer_clk)
138 {
139 unsigned int c = clk_get_rate(timer_clk);
140 void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
141
142 imx_delay_timer.read_current_timer = &imx_read_current_timer;
143 imx_delay_timer.freq = c;
144 register_current_timer_delay(&imx_delay_timer);
145
146 sched_clock_reg = reg;
147
148 sched_clock_register(mxc_read_sched_clock, 32, c);
149 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
150 clocksource_mmio_readl_up);
151 }
152
153 /* clock event */
154
155 static int mx1_2_set_next_event(unsigned long evt,
156 struct clock_event_device *unused)
157 {
158 unsigned long tcmp;
159
160 tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
161
162 __raw_writel(tcmp, timer_base + MX1_2_TCMP);
163
164 return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
165 -ETIME : 0;
166 }
167
168 static int v2_set_next_event(unsigned long evt,
169 struct clock_event_device *unused)
170 {
171 unsigned long tcmp;
172
173 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
174
175 __raw_writel(tcmp, timer_base + V2_TCMP);
176
177 return evt < 0x7fffffff &&
178 (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
179 -ETIME : 0;
180 }
181
182 #ifdef DEBUG
183 static const char *clock_event_mode_label[] = {
184 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
185 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
186 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
187 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
188 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
189 };
190 #endif /* DEBUG */
191
192 static void mxc_set_mode(enum clock_event_mode mode,
193 struct clock_event_device *evt)
194 {
195 unsigned long flags;
196
197 /*
198 * The timer interrupt generation is disabled at least
199 * for enough time to call mxc_set_next_event()
200 */
201 local_irq_save(flags);
202
203 /* Disable interrupt in GPT module */
204 gpt_irq_disable();
205
206 if (mode != clockevent_mode) {
207 /* Set event time into far-far future */
208 if (timer_is_v2())
209 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
210 timer_base + V2_TCMP);
211 else
212 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
213 timer_base + MX1_2_TCMP);
214
215 /* Clear pending interrupt */
216 gpt_irq_acknowledge();
217 }
218
219 #ifdef DEBUG
220 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
221 clock_event_mode_label[clockevent_mode],
222 clock_event_mode_label[mode]);
223 #endif /* DEBUG */
224
225 /* Remember timer mode */
226 clockevent_mode = mode;
227 local_irq_restore(flags);
228
229 switch (mode) {
230 case CLOCK_EVT_MODE_PERIODIC:
231 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
232 "supported for i.MX\n");
233 break;
234 case CLOCK_EVT_MODE_ONESHOT:
235 /*
236 * Do not put overhead of interrupt enable/disable into
237 * mxc_set_next_event(), the core has about 4 minutes
238 * to call mxc_set_next_event() or shutdown clock after
239 * mode switching
240 */
241 local_irq_save(flags);
242 gpt_irq_enable();
243 local_irq_restore(flags);
244 break;
245 case CLOCK_EVT_MODE_SHUTDOWN:
246 case CLOCK_EVT_MODE_UNUSED:
247 case CLOCK_EVT_MODE_RESUME:
248 /* Left event sources disabled, no more interrupts appear */
249 break;
250 }
251 }
252
253 /*
254 * IRQ handler for the timer
255 */
256 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
257 {
258 struct clock_event_device *evt = &clockevent_mxc;
259 uint32_t tstat;
260
261 if (timer_is_v2())
262 tstat = __raw_readl(timer_base + V2_TSTAT);
263 else
264 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
265
266 gpt_irq_acknowledge();
267
268 evt->event_handler(evt);
269
270 return IRQ_HANDLED;
271 }
272
273 static struct irqaction mxc_timer_irq = {
274 .name = "i.MX Timer Tick",
275 .flags = IRQF_TIMER | IRQF_IRQPOLL,
276 .handler = mxc_timer_interrupt,
277 };
278
279 static struct clock_event_device clockevent_mxc = {
280 .name = "mxc_timer1",
281 .features = CLOCK_EVT_FEAT_ONESHOT,
282 .set_mode = mxc_set_mode,
283 .set_next_event = mx1_2_set_next_event,
284 .rating = 200,
285 };
286
287 static int __init mxc_clockevent_init(struct clk *timer_clk)
288 {
289 if (timer_is_v2())
290 clockevent_mxc.set_next_event = v2_set_next_event;
291
292 clockevent_mxc.cpumask = cpumask_of(0);
293 clockevents_config_and_register(&clockevent_mxc,
294 clk_get_rate(timer_clk),
295 0xff, 0xfffffffe);
296
297 return 0;
298 }
299
300 static void __init _mxc_timer_init(int irq,
301 struct clk *clk_per, struct clk *clk_ipg)
302 {
303 uint32_t tctl_val;
304
305 if (IS_ERR(clk_per)) {
306 pr_err("i.MX timer: unable to get clk\n");
307 return;
308 }
309
310 if (!IS_ERR(clk_ipg))
311 clk_prepare_enable(clk_ipg);
312
313 clk_prepare_enable(clk_per);
314
315 /*
316 * Initialise to a known state (all timers off, and timing reset)
317 */
318
319 __raw_writel(0, timer_base + MXC_TCTL);
320 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
321
322 if (timer_is_v2()) {
323 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
324 if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) {
325 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
326 if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
327 /* 24 / 8 = 3 MHz */
328 __raw_writel(7 << V2_TPRER_PRE24M,
329 timer_base + MXC_TPRER);
330 tctl_val |= V2_TCTL_24MEN;
331 }
332 } else {
333 tctl_val |= V2_TCTL_CLK_PER;
334 }
335 } else {
336 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
337 }
338
339 __raw_writel(tctl_val, timer_base + MXC_TCTL);
340
341 /* init and register the timer to the framework */
342 mxc_clocksource_init(clk_per);
343 mxc_clockevent_init(clk_per);
344
345 /* Make irqs happen */
346 setup_irq(irq, &mxc_timer_irq);
347 }
348
349 void __init mxc_timer_init(unsigned long pbase, int irq)
350 {
351 struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
352 struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
353
354 timer_base = ioremap(pbase, SZ_4K);
355 BUG_ON(!timer_base);
356
357 _mxc_timer_init(irq, clk_per, clk_ipg);
358 }
359
360 static void __init mxc_timer_init_dt(struct device_node *np)
361 {
362 struct clk *clk_per, *clk_ipg;
363 int irq;
364
365 if (timer_base)
366 return;
367
368 timer_base = of_iomap(np, 0);
369 WARN_ON(!timer_base);
370 irq = irq_of_parse_and_map(np, 0);
371
372 clk_ipg = of_clk_get_by_name(np, "ipg");
373
374 /* Try osc_per first, and fall back to per otherwise */
375 clk_per = of_clk_get_by_name(np, "osc_per");
376 if (IS_ERR(clk_per))
377 clk_per = of_clk_get_by_name(np, "per");
378
379 _mxc_timer_init(irq, clk_per, clk_ipg);
380 }
381 CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
382 CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
383 CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
384 CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
385 CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
386 CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
387 CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
388 CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);
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