arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/string.h>
  17 #include <linux/device.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/kmi.h>
  20 #include <linux/amba/clcd.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/io.h>
  23 #include <linux/irqchip/versatile-fpga.h>
  24 #include <linux/gfp.h>
  25 #include <linux/mtd/physmap.h>
  26 #include <linux/platform_data/clk-integrator.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include <mach/hardware.h>
  33 #include <mach/platform.h>
  34 #include <asm/setup.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst.h>
  38
  39 #include <mach/lm.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/time.h>
  45
  46 #include <asm/hardware/timer-sp.h>
  47
  48 #include <plat/clcd.h>
  49 #include <plat/sched_clock.h>
  50
  51 #include "cm.h"
  52 #include "common.h"
  53
  54 /* Base address to the CP controller */
  55 static void __iomem *intcp_con_base;
  56
  57 #define INTCP_PA_FLASH_BASE             0x24000000
  58
  59 #define INTCP_PA_CLCD_BASE              0xc0000000
  60
  61 #define INTCP_FLASHPROG                 0x04
  62 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  63 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  64
  65 /*
  66  * Logical      Physical
  67  * f1000000     10000000        Core module registers
  68  * f1100000     11000000        System controller registers
  69  * f1200000     12000000        EBI registers
  70  * f1300000     13000000        Counter/Timer
  71  * f1400000     14000000        Interrupt controller
  72  * f1600000     16000000        UART 0
  73  * f1700000     17000000        UART 1
  74  * f1a00000     1a000000        Debug LEDs
  75  * fc900000     c9000000        GPIO
  76  * fca00000     ca000000        SIC
  77  * fcb00000     cb000000        CP system control
  78  */
  79
  80 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
  81         {
  82                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  83                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  84                 .length         = SZ_4K,
  85                 .type           = MT_DEVICE
  86         }, {
  87                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  88                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  89                 .length         = SZ_4K,
  90                 .type           = MT_DEVICE
  91         }, {
  92                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  93                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  94                 .length         = SZ_4K,
  95                 .type           = MT_DEVICE
  96         }, {
  97                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  98                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE
 101         }, {
 102                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 103                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE
 106         }, {
 107                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 108                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 109                 .length         = SZ_4K,
 110                 .type           = MT_DEVICE
 111         }, {
 112                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
 113                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 114                 .length         = SZ_4K,
 115                 .type           = MT_DEVICE
 116         }, {
 117                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 118                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE
 121         }
 122 };
 123
 124 static void __init intcp_map_io(void)
 125 {
 126         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 127 }
 128
 129 /*
 130  * Flash handling.
 131  */
 132 static int intcp_flash_init(struct platform_device *dev)
 133 {
 134         u32 val;
 135
 136         val = readl(intcp_con_base + INTCP_FLASHPROG);
 137         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 138         writel(val, intcp_con_base + INTCP_FLASHPROG);
 139
 140         return 0;
 141 }
 142
 143 static void intcp_flash_exit(struct platform_device *dev)
 144 {
 145         u32 val;
 146
 147         val = readl(intcp_con_base + INTCP_FLASHPROG);
 148         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 149         writel(val, intcp_con_base + INTCP_FLASHPROG);
 150 }
 151
 152 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 153 {
 154         u32 val;
 155
 156         val = readl(intcp_con_base + INTCP_FLASHPROG);
 157         if (on)
 158                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 159         else
 160                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 161         writel(val, intcp_con_base + INTCP_FLASHPROG);
 162 }
 163
 164 static struct physmap_flash_data intcp_flash_data = {
 165         .width          = 4,
 166         .init           = intcp_flash_init,
 167         .exit           = intcp_flash_exit,
 168         .set_vpp        = intcp_flash_set_vpp,
 169 };
 170
 171 /*
 172  * It seems that the card insertion interrupt remains active after
 173  * we've acknowledged it.  We therefore ignore the interrupt, and
 174  * rely on reading it from the SIC.  This also means that we must
 175  * clear the latched interrupt.
 176  */
 177 static unsigned int mmc_status(struct device *dev)
 178 {
 179         unsigned int status = readl(__io_address(0xca000000 + 4));
 180         writel(8, intcp_con_base + 8);
 181
 182         return status & 8;
 183 }
 184
 185 static struct mmci_platform_data mmc_data = {
 186         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 187         .status         = mmc_status,
 188         .gpio_wp        = -1,
 189         .gpio_cd        = -1,
 190 };
 191
 192 /*
 193  * CLCD support
 194  */
 195 /*
 196  * Ensure VGA is selected.
 197  */
 198 static void cp_clcd_enable(struct clcd_fb *fb)
 199 {
 200         struct fb_var_screeninfo *var = &fb->fb.var;
 201         u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
 202                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
 203
 204         if (var->bits_per_pixel <= 8 ||
 205             (var->bits_per_pixel == 16 && var->green.length == 5))
 206                 /* Pseudocolor, RGB555, BGR555 */
 207                 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
 208         else if (fb->fb.var.bits_per_pixel <= 16)
 209                 /* truecolor RGB565 */
 210                 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
 211         else
 212                 val = 0; /* no idea for this, don't trust the docs */
 213
 214         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 215                    CM_CTRL_LCDEN0|
 216                    CM_CTRL_LCDEN1|
 217                    CM_CTRL_STATIC1|
 218                    CM_CTRL_STATIC2|
 219                    CM_CTRL_STATIC|
 220                    CM_CTRL_n24BITEN, val);
 221 }
 222
 223 static int cp_clcd_setup(struct clcd_fb *fb)
 224 {
 225         fb->panel = versatile_clcd_get_panel("VGA");
 226         if (!fb->panel)
 227                 return -EINVAL;
 228
 229         return versatile_clcd_setup_dma(fb, SZ_1M);
 230 }
 231
 232 static struct clcd_board clcd_data = {
 233         .name           = "Integrator/CP",
 234         .caps           = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
 235         .check          = clcdfb_check,
 236         .decode         = clcdfb_decode,
 237         .enable         = cp_clcd_enable,
 238         .setup          = cp_clcd_setup,
 239         .mmap           = versatile_clcd_mmap_dma,
 240         .remove         = versatile_clcd_remove_dma,
 241 };
 242
 243 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 244
 245 static void __init intcp_init_early(void)
 246 {
 247 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
 248         versatile_sched_clock_init(REFCOUNTER, 24000000);
 249 #endif
 250 }
 251
 252 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 253         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 254         { /* Sentinel */ }
 255 };
 256
 257 static void __init intcp_init_irq_of(void)
 258 {
 259         cm_init();
 260         of_irq_init(fpga_irq_of_match);
 261         integrator_clk_init(true);
 262 }
 263
 264 /*
 265  * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 266  * and enforce the bus names since these are used for clock lookups.
 267  */
 268 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 269         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 270                 "rtc", NULL),
 271         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 272                 "uart0", NULL),
 273         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 274                 "uart1", NULL),
 275         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 276                 "kmi0", NULL),
 277         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 278                 "kmi1", NULL),
 279         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
 280                 "mmci", &mmc_data),
 281         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
 282                 "aaci", &mmc_data),
 283         OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 284                 "clcd", &clcd_data),
 285         OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
 286                 "physmap-flash", &intcp_flash_data),
 287         { /* sentinel */ },
 288 };
 289
 290 static const struct of_device_id intcp_syscon_match[] = {
 291         { .compatible = "arm,integrator-cp-syscon"},
 292         { },
 293 };
 294
 295 static void __init intcp_init_of(void)
 296 {
 297         struct device_node *root;
 298         struct device_node *cpcon;
 299         struct device *parent;
 300         struct soc_device *soc_dev;
 301         struct soc_device_attribute *soc_dev_attr;
 302         u32 intcp_sc_id;
 303         int err;
 304
 305         /* Here we create an SoC device for the root node */
 306         root = of_find_node_by_path("/");
 307         if (!root)
 308                 return;
 309
 310         cpcon = of_find_matching_node(root, intcp_syscon_match);
 311         if (!cpcon)
 312                 return;
 313
 314         intcp_con_base = of_iomap(cpcon, 0);
 315         if (!intcp_con_base)
 316                 return;
 317
 318         intcp_sc_id = readl(intcp_con_base);
 319
 320         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 321         if (!soc_dev_attr)
 322                 return;
 323
 324         err = of_property_read_string(root, "compatible",
 325                                       &soc_dev_attr->soc_id);
 326         if (err)
 327                 return;
 328         err = of_property_read_string(root, "model", &soc_dev_attr->machine);
 329         if (err)
 330                 return;
 331         soc_dev_attr->family = "Integrator";
 332         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
 333                                            'A' + (intcp_sc_id & 0x0f));
 334
 335         soc_dev = soc_device_register(soc_dev_attr);
 336         if (IS_ERR(soc_dev)) {
 337                 kfree(soc_dev_attr->revision);
 338                 kfree(soc_dev_attr);
 339                 return;
 340         }
 341
 342         parent = soc_device_to_device(soc_dev);
 343         integrator_init_sysfs(parent, intcp_sc_id);
 344         of_platform_populate(root, of_default_bus_match_table,
 345                         intcp_auxdata_lookup, parent);
 346 }
 347
 348 static const char * intcp_dt_board_compat[] = {
 349         "arm,integrator-cp",
 350         NULL,
 351 };
 352
 353 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 354         .reserve        = integrator_reserve,
 355         .map_io         = intcp_map_io,
 356         .init_early     = intcp_init_early,
 357         .init_irq       = intcp_init_irq_of,
 358         .handle_irq     = fpga_handle_irq,
 359         .init_machine   = intcp_init_of,
 360         .restart        = integrator_restart,
 361         .dt_compat      = intcp_dt_board_compat,
 362 MACHINE_END