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ARM: kirkwood: Trim excess #includes in board-dnskw.c
[deliverable/linux.git] / arch / arm / mach-integrator / integrator_cp.c
1 /*
2 * linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/device.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/amba/mmci.h>
22 #include <linux/io.h>
23 #include <linux/gfp.h>
24 #include <linux/mtd/physmap.h>
25 #include <linux/platform_data/clk-integrator.h>
26
27 #include <mach/hardware.h>
28 #include <mach/platform.h>
29 #include <asm/setup.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware/arm_timer.h>
32 #include <asm/hardware/icst.h>
33
34 #include <mach/cm.h>
35 #include <mach/lm.h>
36 #include <mach/irqs.h>
37
38 #include <asm/mach/arch.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/time.h>
42
43 #include <asm/hardware/timer-sp.h>
44
45 #include <plat/clcd.h>
46 #include <plat/fpga-irq.h>
47 #include <plat/sched_clock.h>
48
49 #include "common.h"
50
51 #define INTCP_PA_FLASH_BASE 0x24000000
52 #define INTCP_FLASH_SIZE SZ_32M
53
54 #define INTCP_PA_CLCD_BASE 0xc0000000
55
56 #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
57 #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
58 #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
59
60 #define INTCP_ETH_SIZE 0x10
61
62 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
63 #define INTCP_FLASHPROG 0x04
64 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
65 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
66
67 /*
68 * Logical Physical
69 * f1000000 10000000 Core module registers
70 * f1100000 11000000 System controller registers
71 * f1200000 12000000 EBI registers
72 * f1300000 13000000 Counter/Timer
73 * f1400000 14000000 Interrupt controller
74 * f1600000 16000000 UART 0
75 * f1700000 17000000 UART 1
76 * f1a00000 1a000000 Debug LEDs
77 * fc900000 c9000000 GPIO
78 * fca00000 ca000000 SIC
79 * fcb00000 cb000000 CP system control
80 */
81
82 static struct map_desc intcp_io_desc[] __initdata = {
83 {
84 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
85 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE
88 }, {
89 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
90 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
91 .length = SZ_4K,
92 .type = MT_DEVICE
93 }, {
94 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
106 .length = SZ_4K,
107 .type = MT_DEVICE
108 }, {
109 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
111 .length = SZ_4K,
112 .type = MT_DEVICE
113 }, {
114 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
116 .length = SZ_4K,
117 .type = MT_DEVICE
118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
124 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
125 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }, {
129 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
130 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
131 .length = SZ_4K,
132 .type = MT_DEVICE
133 }, {
134 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
135 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
136 .length = SZ_4K,
137 .type = MT_DEVICE
138 }
139 };
140
141 static void __init intcp_map_io(void)
142 {
143 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
144 }
145
146 static void __init intcp_init_irq(void)
147 {
148 u32 pic_mask, cic_mask, sic_mask;
149
150 /* These masks are for the HW IRQ registers */
151 pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
152 pic_mask |= (~((~0u) << (29 - 22))) << 22;
153 cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
154 sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
155
156 /*
157 * Disable all interrupt sources
158 */
159 writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
160 writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
161 writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
162 writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
163 writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
164 writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
165
166 fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
167 -1, pic_mask, NULL);
168
169 fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
170 -1, cic_mask, NULL);
171
172 fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
173 IRQ_CP_CPPLDINT, sic_mask, NULL);
174 integrator_clk_init(true);
175 }
176
177 /*
178 * Flash handling.
179 */
180 static int intcp_flash_init(struct platform_device *dev)
181 {
182 u32 val;
183
184 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
185 val |= CINTEGRATOR_FLASHPROG_FLWREN;
186 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
187
188 return 0;
189 }
190
191 static void intcp_flash_exit(struct platform_device *dev)
192 {
193 u32 val;
194
195 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
196 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
197 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
198 }
199
200 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
201 {
202 u32 val;
203
204 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
205 if (on)
206 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
207 else
208 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
209 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
210 }
211
212 static struct physmap_flash_data intcp_flash_data = {
213 .width = 4,
214 .init = intcp_flash_init,
215 .exit = intcp_flash_exit,
216 .set_vpp = intcp_flash_set_vpp,
217 };
218
219 static struct resource intcp_flash_resource = {
220 .start = INTCP_PA_FLASH_BASE,
221 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
222 .flags = IORESOURCE_MEM,
223 };
224
225 static struct platform_device intcp_flash_device = {
226 .name = "physmap-flash",
227 .id = 0,
228 .dev = {
229 .platform_data = &intcp_flash_data,
230 },
231 .num_resources = 1,
232 .resource = &intcp_flash_resource,
233 };
234
235 static struct resource smc91x_resources[] = {
236 [0] = {
237 .start = INTEGRATOR_CP_ETH_BASE,
238 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 [1] = {
242 .start = IRQ_CP_ETHINT,
243 .end = IRQ_CP_ETHINT,
244 .flags = IORESOURCE_IRQ,
245 },
246 };
247
248 static struct platform_device smc91x_device = {
249 .name = "smc91x",
250 .id = 0,
251 .num_resources = ARRAY_SIZE(smc91x_resources),
252 .resource = smc91x_resources,
253 };
254
255 static struct platform_device *intcp_devs[] __initdata = {
256 &intcp_flash_device,
257 &smc91x_device,
258 };
259
260 /*
261 * It seems that the card insertion interrupt remains active after
262 * we've acknowledged it. We therefore ignore the interrupt, and
263 * rely on reading it from the SIC. This also means that we must
264 * clear the latched interrupt.
265 */
266 static unsigned int mmc_status(struct device *dev)
267 {
268 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
269 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
270
271 return status & 8;
272 }
273
274 static struct mmci_platform_data mmc_data = {
275 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
276 .status = mmc_status,
277 .gpio_wp = -1,
278 .gpio_cd = -1,
279 };
280
281 #define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
282 #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
283
284 static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
285 INTEGRATOR_CP_MMC_IRQS, &mmc_data);
286
287 static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
288 INTEGRATOR_CP_AACI_IRQS, NULL);
289
290
291 /*
292 * CLCD support
293 */
294 /*
295 * Ensure VGA is selected.
296 */
297 static void cp_clcd_enable(struct clcd_fb *fb)
298 {
299 struct fb_var_screeninfo *var = &fb->fb.var;
300 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
301
302 if (var->bits_per_pixel <= 8 ||
303 (var->bits_per_pixel == 16 && var->green.length == 5))
304 /* Pseudocolor, RGB555, BGR555 */
305 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
306 else if (fb->fb.var.bits_per_pixel <= 16)
307 /* truecolor RGB565 */
308 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
309 else
310 val = 0; /* no idea for this, don't trust the docs */
311
312 cm_control(CM_CTRL_LCDMUXSEL_MASK|
313 CM_CTRL_LCDEN0|
314 CM_CTRL_LCDEN1|
315 CM_CTRL_STATIC1|
316 CM_CTRL_STATIC2|
317 CM_CTRL_STATIC|
318 CM_CTRL_n24BITEN, val);
319 }
320
321 static int cp_clcd_setup(struct clcd_fb *fb)
322 {
323 fb->panel = versatile_clcd_get_panel("VGA");
324 if (!fb->panel)
325 return -EINVAL;
326
327 return versatile_clcd_setup_dma(fb, SZ_1M);
328 }
329
330 static struct clcd_board clcd_data = {
331 .name = "Integrator/CP",
332 .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
333 .check = clcdfb_check,
334 .decode = clcdfb_decode,
335 .enable = cp_clcd_enable,
336 .setup = cp_clcd_setup,
337 .mmap = versatile_clcd_mmap_dma,
338 .remove = versatile_clcd_remove_dma,
339 };
340
341 static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
342 { IRQ_CP_CLCDCINT }, &clcd_data);
343
344 static struct amba_device *amba_devs[] __initdata = {
345 &mmc_device,
346 &aaci_device,
347 &clcd_device,
348 };
349
350 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
351
352 static void __init intcp_init_early(void)
353 {
354 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
355 versatile_sched_clock_init(REFCOUNTER, 24000000);
356 #endif
357 }
358
359 static void __init intcp_init(void)
360 {
361 int i;
362
363 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
364
365 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
366 struct amba_device *d = amba_devs[i];
367 amba_device_register(d, &iomem_resource);
368 }
369 }
370
371 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
372 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
373 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
374
375 static void __init intcp_timer_init(void)
376 {
377 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
378 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
379 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
380
381 sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
382 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
383 }
384
385 static struct sys_timer cp_timer = {
386 .init = intcp_timer_init,
387 };
388
389 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
390 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
391 .atag_offset = 0x100,
392 .reserve = integrator_reserve,
393 .map_io = intcp_map_io,
394 .nr_irqs = NR_IRQS_INTEGRATOR_CP,
395 .init_early = intcp_init_early,
396 .init_irq = intcp_init_irq,
397 .handle_irq = fpga_handle_irq,
398 .timer = &cp_timer,
399 .init_machine = intcp_init,
400 .restart = integrator_restart,
401 MACHINE_END
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