arch/arm/mach-iop3xx/iop321-setup.c

   1 /*
   2  * linux/arch/arm/mach-iop3xx/iop321-setup.c
   3  *
   4  * Author: Nicolas Pitre <nico@cam.org>
   5  * Copyright (C) 2001 MontaVista Software, Inc.
   6  * Copyright (C) 2004 Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  */
  13 #include <linux/mm.h>
  14 #include <linux/init.h>
  15 #include <linux/config.h>
  16 #include <linux/init.h>
  17 #include <linux/major.h>
  18 #include <linux/fs.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/serial.h>
  21 #include <linux/tty.h>
  22 #include <linux/serial_core.h>
  23
  24 #include <asm/io.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/page.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/setup.h>
  29 #include <asm/system.h>
  30 #include <asm/memory.h>
  31 #include <asm/hardware.h>
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/arch.h>
  34
  35 #define IOP321_UART_XTAL 1843200
  36
  37 /*
  38  * Standard IO mapping for all IOP321 based systems
  39  */
  40 static struct map_desc iop321_std_desc[] __initdata = {
  41          {      /* mem mapped registers */
  42                 .virtual        = IOP321_VIRT_MEM_BASE,
  43                 .pfn            = __phys_to_pfn(IOP321_PHYS_MEM_BASE),
  44                 .length         = 0x00002000,
  45                 .type           = MT_DEVICE
  46          }, {   /* PCI IO space */
  47                 .virtual        = IOP321_PCI_LOWER_IO_VA,
  48                 .pfn            = __phys_to_pfn(IOP321_PCI_LOWER_IO_PA),
  49                 .length         = IOP321_PCI_IO_WINDOW_SIZE,
  50                 .type           = MT_DEVICE
  51          }
  52 };
  53
  54 #ifdef CONFIG_ARCH_IQ80321
  55 #define UARTBASE IQ80321_UART
  56 #define IRQ_UART IRQ_IQ80321_UART
  57 #endif
  58
  59 #ifdef CONFIG_ARCH_IQ31244
  60 #define UARTBASE IQ31244_UART
  61 #define IRQ_UART IRQ_IQ31244_UART
  62 #endif
  63
  64 static struct uart_port iop321_serial_ports[] = {
  65         {
  66                 .membase        = (char*)(UARTBASE),
  67                 .mapbase        = (UARTBASE),
  68                 .irq            = IRQ_UART,
  69                 .flags          = UPF_SKIP_TEST,
  70                 .iotype         = UPIO_MEM,
  71                 .regshift       = 0,
  72                 .uartclk        = IOP321_UART_XTAL,
  73                 .line           = 0,
  74                 .type           = PORT_16550A,
  75                 .fifosize       = 16
  76         }
  77 };
  78
  79 static struct resource iop32x_i2c_0_resources[] = {
  80         [0] = {
  81                 .start = 0xfffff680,
  82                 .end = 0xfffff698,
  83                 .flags = IORESOURCE_MEM,
  84         },
  85         [1] = {
  86                 .start = IRQ_IOP321_I2C_0,
  87                 .end = IRQ_IOP321_I2C_0,
  88                 .flags = IORESOURCE_IRQ
  89         }
  90 };
  91
  92 static struct resource iop32x_i2c_1_resources[] = {
  93         [0] = {
  94                 .start = 0xfffff6a0,
  95                 .end = 0xfffff6b8,
  96                 .flags = IORESOURCE_MEM,
  97         },
  98         [1] = {
  99                 .start = IRQ_IOP321_I2C_1,
 100                 .end = IRQ_IOP321_I2C_1,
 101                 .flags = IORESOURCE_IRQ
 102         }
 103 };
 104
 105 static struct platform_device iop32x_i2c_0_controller = {
 106         .name = "IOP3xx-I2C",
 107         .id = 0,
 108         .num_resources = 2,
 109         .resource = iop32x_i2c_0_resources
 110 };
 111
 112 static struct platform_device iop32x_i2c_1_controller = {
 113         .name = "IOP3xx-I2C",
 114         .id = 1,
 115         .num_resources = 2,
 116         .resource = iop32x_i2c_1_resources
 117 };
 118
 119 static struct platform_device *iop32x_devices[] __initdata = {
 120         &iop32x_i2c_0_controller,
 121         &iop32x_i2c_1_controller
 122 };
 123
 124 void __init iop32x_init(void)
 125 {
 126         if(iop_is_321())
 127         {
 128                 platform_add_devices(iop32x_devices,
 129                                 ARRAY_SIZE(iop32x_devices));
 130         }
 131 }
 132
 133 void __init iop321_map_io(void)
 134 {
 135         iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc));
 136         early_serial_setup(&iop321_serial_ports[0]);
 137 }
 138
 139 #ifdef CONFIG_ARCH_IQ80321
 140 extern void iq80321_map_io(void);
 141 extern struct sys_timer iop321_timer;
 142 extern void iop321_init_time(void);
 143 #endif
 144
 145 #ifdef CONFIG_ARCH_IQ31244
 146 extern void iq31244_map_io(void);
 147 extern struct sys_timer iop321_timer;
 148 extern void iop321_init_time(void);
 149 #endif
 150
 151 #if defined(CONFIG_ARCH_IQ80321)
 152 MACHINE_START(IQ80321, "Intel IQ80321")
 153         /* Maintainer: Intel Corporation */
 154         .phys_ram       = PHYS_OFFSET,
 155         .phys_io        = IQ80321_UART,
 156         .io_pg_offst    = ((IQ80321_UART) >> 18) & 0xfffc,
 157         .map_io         = iq80321_map_io,
 158         .init_irq       = iop321_init_irq,
 159         .timer          = &iop321_timer,
 160         .boot_params    = 0xa0000100,
 161         .init_machine   = iop32x_init,
 162 MACHINE_END
 163 #elif defined(CONFIG_ARCH_IQ31244)
 164 MACHINE_START(IQ31244, "Intel IQ31244")
 165         /* Maintainer: Intel Corp. */
 166         .phys_ram       = PHYS_OFFSET,
 167         .phys_io        = IQ31244_UART,
 168         .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
 169         .map_io         = iq31244_map_io,
 170         .init_irq       = iop321_init_irq,
 171         .timer          = &iop321_timer,
 172         .boot_params    = 0xa0000100,
 173         .init_machine   = iop32x_init,
 174 MACHINE_END
 175 #else
 176 #error No machine descriptor defined for this IOP3XX implementation
 177 #endif