arch/arm/mach-ixp4xx/goramo_mlr.c

   1 /*
   2  * Goramo MultiLink router platform code
   3  * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
   4  */
   5
   6 #include <linux/delay.h>
   7 #include <linux/hdlc.h>
   8 #include <linux/i2c-gpio.h>
   9 #include <linux/io.h>
  10 #include <linux/irq.h>
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/serial_8250.h>
  14 #include <asm/mach-types.h>
  15 #include <asm/mach/arch.h>
  16 #include <asm/mach/flash.h>
  17 #include <asm/mach/pci.h>
  18 #include <asm/system_info.h>
  19
  20 #define IXP4XX_GPIO_OUT                 0x1
  21 #define IXP4XX_GPIO_IN                  0x2
  22
  23 void gpio_line_config(u8 line, u32 direction);
  24 void gpio_line_get(u8 line, int *value);
  25 void gpio_line_set(u8 line, int value);
  26
  27 #define SLOT_ETHA               0x0B    /* IDSEL = AD21 */
  28 #define SLOT_ETHB               0x0C    /* IDSEL = AD20 */
  29 #define SLOT_MPCI               0x0D    /* IDSEL = AD19 */
  30 #define SLOT_NEC                0x0E    /* IDSEL = AD18 */
  31
  32 /* GPIO lines */
  33 #define GPIO_SCL                0
  34 #define GPIO_SDA                1
  35 #define GPIO_STR                2
  36 #define GPIO_IRQ_NEC            3
  37 #define GPIO_IRQ_ETHA           4
  38 #define GPIO_IRQ_ETHB           5
  39 #define GPIO_HSS0_DCD_N         6
  40 #define GPIO_HSS1_DCD_N         7
  41 #define GPIO_UART0_DCD          8
  42 #define GPIO_UART1_DCD          9
  43 #define GPIO_HSS0_CTS_N         10
  44 #define GPIO_HSS1_CTS_N         11
  45 #define GPIO_IRQ_MPCI           12
  46 #define GPIO_HSS1_RTS_N         13
  47 #define GPIO_HSS0_RTS_N         14
  48 /* GPIO15 is not connected */
  49
  50 /* Control outputs from 74HC4094 */
  51 #define CONTROL_HSS0_CLK_INT    0
  52 #define CONTROL_HSS1_CLK_INT    1
  53 #define CONTROL_HSS0_DTR_N      2
  54 #define CONTROL_HSS1_DTR_N      3
  55 #define CONTROL_EXT             4
  56 #define CONTROL_AUTO_RESET      5
  57 #define CONTROL_PCI_RESET_N     6
  58 #define CONTROL_EEPROM_WC_N     7
  59
  60 /* offsets from start of flash ROM = 0x50000000 */
  61 #define CFG_ETH0_ADDRESS        0x40 /* 6 bytes */
  62 #define CFG_ETH1_ADDRESS        0x46 /* 6 bytes */
  63 #define CFG_REV                 0x4C /* u32 */
  64 #define CFG_SDRAM_SIZE          0x50 /* u32 */
  65 #define CFG_SDRAM_CONF          0x54 /* u32 */
  66 #define CFG_SDRAM_MODE          0x58 /* u32 */
  67 #define CFG_SDRAM_REFRESH       0x5C /* u32 */
  68
  69 #define CFG_HW_BITS             0x60 /* u32 */
  70 #define  CFG_HW_USB_PORTS       0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
  71 #define  CFG_HW_HAS_PCI_SLOT    0x00000008
  72 #define  CFG_HW_HAS_ETH0        0x00000010
  73 #define  CFG_HW_HAS_ETH1        0x00000020
  74 #define  CFG_HW_HAS_HSS0        0x00000040
  75 #define  CFG_HW_HAS_HSS1        0x00000080
  76 #define  CFG_HW_HAS_UART0       0x00000100
  77 #define  CFG_HW_HAS_UART1       0x00000200
  78 #define  CFG_HW_HAS_EEPROM      0x00000400
  79
  80 #define FLASH_CMD_READ_ARRAY    0xFF
  81 #define FLASH_CMD_READ_ID       0x90
  82 #define FLASH_SER_OFF           0x102 /* 0x81 in 16-bit mode */
  83
  84 static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
  85 static u8 control_value;
  86
  87 static void set_scl(u8 value)
  88 {
  89         gpio_line_set(GPIO_SCL, !!value);
  90         udelay(3);
  91 }
  92
  93 static void set_sda(u8 value)
  94 {
  95         gpio_line_set(GPIO_SDA, !!value);
  96         udelay(3);
  97 }
  98
  99 static void set_str(u8 value)
 100 {
 101         gpio_line_set(GPIO_STR, !!value);
 102         udelay(3);
 103 }
 104
 105 static inline void set_control(int line, int value)
 106 {
 107         if (value)
 108                 control_value |=  (1 << line);
 109         else
 110                 control_value &= ~(1 << line);
 111 }
 112
 113
 114 static void output_control(void)
 115 {
 116         int i;
 117
 118         gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
 119         gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
 120
 121         for (i = 0; i < 8; i++) {
 122                 set_scl(0);
 123                 set_sda(control_value & (0x80 >> i)); /* MSB first */
 124                 set_scl(1);     /* active edge */
 125         }
 126
 127         set_str(1);
 128         set_str(0);
 129
 130         set_scl(0);
 131         set_sda(1);             /* Be ready for START */
 132         set_scl(1);
 133 }
 134
 135
 136 static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
 137
 138 static int hss_set_clock(int port, unsigned int clock_type)
 139 {
 140         int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
 141
 142         switch (clock_type) {
 143         case CLOCK_DEFAULT:
 144         case CLOCK_EXT:
 145                 set_control(ctrl_int, 0);
 146                 output_control();
 147                 return CLOCK_EXT;
 148
 149         case CLOCK_INT:
 150                 set_control(ctrl_int, 1);
 151                 output_control();
 152                 return CLOCK_INT;
 153
 154         default:
 155                 return -EINVAL;
 156         }
 157 }
 158
 159 static irqreturn_t hss_dcd_irq(int irq, void *pdev)
 160 {
 161         int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
 162         gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
 163         set_carrier_cb_tab[port](pdev, !i);
 164         return IRQ_HANDLED;
 165 }
 166
 167
 168 static int hss_open(int port, void *pdev,
 169                     void (*set_carrier_cb)(void *pdev, int carrier))
 170 {
 171         int i, irq;
 172
 173         if (!port)
 174                 irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
 175         else
 176                 irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
 177
 178         gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
 179         set_carrier_cb(pdev, !i);
 180
 181         set_carrier_cb_tab[!!port] = set_carrier_cb;
 182
 183         if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
 184                 printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
 185                        irq, i);
 186                 return i;
 187         }
 188
 189         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
 190         output_control();
 191         gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
 192         return 0;
 193 }
 194
 195 static void hss_close(int port, void *pdev)
 196 {
 197         free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
 198                  IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
 199         set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
 200
 201         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
 202         output_control();
 203         gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
 204 }
 205
 206
 207 /* Flash memory */
 208 static struct flash_platform_data flash_data = {
 209         .map_name       = "cfi_probe",
 210         .width          = 2,
 211 };
 212
 213 static struct resource flash_resource = {
 214         .flags          = IORESOURCE_MEM,
 215 };
 216
 217 static struct platform_device device_flash = {
 218         .name           = "IXP4XX-Flash",
 219         .id             = 0,
 220         .dev            = { .platform_data = &flash_data },
 221         .num_resources  = 1,
 222         .resource       = &flash_resource,
 223 };
 224
 225
 226 /* I^2C interface */
 227 static struct i2c_gpio_platform_data i2c_data = {
 228         .sda_pin        = GPIO_SDA,
 229         .scl_pin        = GPIO_SCL,
 230 };
 231
 232 static struct platform_device device_i2c = {
 233         .name           = "i2c-gpio",
 234         .id             = 0,
 235         .dev            = { .platform_data = &i2c_data },
 236 };
 237
 238
 239 /* IXP425 2 UART ports */
 240 static struct resource uart_resources[] = {
 241         {
 242                 .start          = IXP4XX_UART1_BASE_PHYS,
 243                 .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
 244                 .flags          = IORESOURCE_MEM,
 245         },
 246         {
 247                 .start          = IXP4XX_UART2_BASE_PHYS,
 248                 .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
 249                 .flags          = IORESOURCE_MEM,
 250         }
 251 };
 252
 253 static struct plat_serial8250_port uart_data[] = {
 254         {
 255                 .mapbase        = IXP4XX_UART1_BASE_PHYS,
 256                 .membase        = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
 257                         REG_OFFSET,
 258                 .irq            = IRQ_IXP4XX_UART1,
 259                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 260                 .iotype         = UPIO_MEM,
 261                 .regshift       = 2,
 262                 .uartclk        = IXP4XX_UART_XTAL,
 263         },
 264         {
 265                 .mapbase        = IXP4XX_UART2_BASE_PHYS,
 266                 .membase        = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
 267                         REG_OFFSET,
 268                 .irq            = IRQ_IXP4XX_UART2,
 269                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 270                 .iotype         = UPIO_MEM,
 271                 .regshift       = 2,
 272                 .uartclk        = IXP4XX_UART_XTAL,
 273         },
 274         { },
 275 };
 276
 277 static struct platform_device device_uarts = {
 278         .name                   = "serial8250",
 279         .id                     = PLAT8250_DEV_PLATFORM,
 280         .dev.platform_data      = uart_data,
 281         .num_resources          = 2,
 282         .resource               = uart_resources,
 283 };
 284
 285
 286 /* Built-in 10/100 Ethernet MAC interfaces */
 287 static struct eth_plat_info eth_plat[] = {
 288         {
 289                 .phy            = 0,
 290                 .rxq            = 3,
 291                 .txreadyq       = 32,
 292         }, {
 293                 .phy            = 1,
 294                 .rxq            = 4,
 295                 .txreadyq       = 33,
 296         }
 297 };
 298
 299 static struct platform_device device_eth_tab[] = {
 300         {
 301                 .name                   = "ixp4xx_eth",
 302                 .id                     = IXP4XX_ETH_NPEB,
 303                 .dev.platform_data      = eth_plat,
 304         }, {
 305                 .name                   = "ixp4xx_eth",
 306                 .id                     = IXP4XX_ETH_NPEC,
 307                 .dev.platform_data      = eth_plat + 1,
 308         }
 309 };
 310
 311
 312 /* IXP425 2 synchronous serial ports */
 313 static struct hss_plat_info hss_plat[] = {
 314         {
 315                 .set_clock      = hss_set_clock,
 316                 .open           = hss_open,
 317                 .close          = hss_close,
 318                 .txreadyq       = 34,
 319         }, {
 320                 .set_clock      = hss_set_clock,
 321                 .open           = hss_open,
 322                 .close          = hss_close,
 323                 .txreadyq       = 35,
 324         }
 325 };
 326
 327 static struct platform_device device_hss_tab[] = {
 328         {
 329                 .name                   = "ixp4xx_hss",
 330                 .id                     = 0,
 331                 .dev.platform_data      = hss_plat,
 332         }, {
 333                 .name                   = "ixp4xx_hss",
 334                 .id                     = 1,
 335                 .dev.platform_data      = hss_plat + 1,
 336         }
 337 };
 338
 339
 340 static struct platform_device *device_tab[7] __initdata = {
 341         &device_flash,          /* index 0 */
 342 };
 343
 344 static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
 345 {
 346 #ifdef __ARMEB__
 347         return __raw_readb(flash + addr);
 348 #else
 349         return __raw_readb(flash + (addr ^ 3));
 350 #endif
 351 }
 352
 353 static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
 354 {
 355 #ifdef __ARMEB__
 356         return __raw_readw(flash + addr);
 357 #else
 358         return __raw_readw(flash + (addr ^ 2));
 359 #endif
 360 }
 361
 362 static void __init gmlr_init(void)
 363 {
 364         u8 __iomem *flash;
 365         int i, devices = 1; /* flash */
 366
 367         ixp4xx_sys_init();
 368
 369         if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
 370                 printk(KERN_ERR "goramo-mlr: unable to access system"
 371                        " configuration data\n");
 372         else {
 373                 system_rev = __raw_readl(flash + CFG_REV);
 374                 hw_bits = __raw_readl(flash + CFG_HW_BITS);
 375
 376                 for (i = 0; i < ETH_ALEN; i++) {
 377                         eth_plat[0].hwaddr[i] =
 378                                 flash_readb(flash, CFG_ETH0_ADDRESS + i);
 379                         eth_plat[1].hwaddr[i] =
 380                                 flash_readb(flash, CFG_ETH1_ADDRESS + i);
 381                 }
 382
 383                 __raw_writew(FLASH_CMD_READ_ID, flash);
 384                 system_serial_high = flash_readw(flash, FLASH_SER_OFF);
 385                 system_serial_high <<= 16;
 386                 system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
 387                 system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
 388                 system_serial_low <<= 16;
 389                 system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
 390                 __raw_writew(FLASH_CMD_READ_ARRAY, flash);
 391
 392                 iounmap(flash);
 393         }
 394
 395         switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
 396         case CFG_HW_HAS_UART0:
 397                 memset(&uart_data[1], 0, sizeof(uart_data[1]));
 398                 device_uarts.num_resources = 1;
 399                 break;
 400
 401         case CFG_HW_HAS_UART1:
 402                 device_uarts.dev.platform_data = &uart_data[1];
 403                 device_uarts.resource = &uart_resources[1];
 404                 device_uarts.num_resources = 1;
 405                 break;
 406         }
 407         if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
 408                 device_tab[devices++] = &device_uarts; /* max index 1 */
 409
 410         if (hw_bits & CFG_HW_HAS_ETH0)
 411                 device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
 412         if (hw_bits & CFG_HW_HAS_ETH1)
 413                 device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
 414
 415         if (hw_bits & CFG_HW_HAS_HSS0)
 416                 device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
 417         if (hw_bits & CFG_HW_HAS_HSS1)
 418                 device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
 419
 420         if (hw_bits & CFG_HW_HAS_EEPROM)
 421                 device_tab[devices++] = &device_i2c; /* max index 6 */
 422
 423         gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
 424         gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
 425         gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT);
 426         gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT);
 427         gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
 428         gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
 429         gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
 430         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
 431         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
 432
 433         set_control(CONTROL_HSS0_DTR_N, 1);
 434         set_control(CONTROL_HSS1_DTR_N, 1);
 435         set_control(CONTROL_EEPROM_WC_N, 1);
 436         set_control(CONTROL_PCI_RESET_N, 1);
 437         output_control();
 438
 439         msleep(1);            /* Wait for PCI devices to initialize */
 440
 441         flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
 442         flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
 443
 444         platform_add_devices(device_tab, devices);
 445 }
 446
 447
 448 #ifdef CONFIG_PCI
 449 static void __init gmlr_pci_preinit(void)
 450 {
 451         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
 452         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
 453         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
 454         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
 455         ixp4xx_pci_preinit();
 456 }
 457
 458 static void __init gmlr_pci_postinit(void)
 459 {
 460         if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
 461             (hw_bits & CFG_HW_USB_PORTS) < 5) {
 462                 /* need to adjust number of USB ports on NEC chip */
 463                 u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
 464                 if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
 465                         value &= ~7;
 466                         value |= (hw_bits & CFG_HW_USB_PORTS);
 467                         ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
 468                 }
 469         }
 470 }
 471
 472 static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 473 {
 474         switch(slot) {
 475         case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
 476         case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
 477         case SLOT_NEC:  return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
 478         default:        return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
 479         }
 480 }
 481
 482 static struct hw_pci gmlr_hw_pci __initdata = {
 483         .nr_controllers = 1,
 484         .ops            = &ixp4xx_ops,
 485         .preinit        = gmlr_pci_preinit,
 486         .postinit       = gmlr_pci_postinit,
 487         .setup          = ixp4xx_setup,
 488         .map_irq        = gmlr_map_irq,
 489 };
 490
 491 static int __init gmlr_pci_init(void)
 492 {
 493         if (machine_is_goramo_mlr() &&
 494             (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
 495                 pci_common_init(&gmlr_hw_pci);
 496         return 0;
 497 }
 498
 499 subsys_initcall(gmlr_pci_init);
 500 #endif /* CONFIG_PCI */
 501
 502
 503 MACHINE_START(GORAMO_MLR, "MultiLink")
 504         /* Maintainer: Krzysztof Halasa */
 505         .map_io         = ixp4xx_map_io,
 506         .init_early     = ixp4xx_init_early,
 507         .init_irq       = ixp4xx_init_irq,
 508         .init_time      = ixp4xx_timer_init,
 509         .atag_offset    = 0x100,
 510         .init_machine   = gmlr_init,
 511 #if defined(CONFIG_PCI)
 512         .dma_zone_size  = SZ_64M,
 513 #endif
 514         .restart        = ixp4xx_restart,
 515 MACHINE_END