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ARM: mvebu: Staticize mvebu_cpu_reset_init
[deliverable/linux.git] / arch / arm / mach-kirkwood / common.c
1 /*
2 * arch/arm/mach-kirkwood/common.c
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/ata_platform.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/clk-provider.h>
19 #include <linux/spinlock.h>
20 #include <linux/mv643xx_i2c.h>
21 #include <linux/timex.h>
22 #include <linux/kexec.h>
23 #include <linux/reboot.h>
24 #include <net/dsa.h>
25 #include <asm/page.h>
26 #include <asm/mach/map.h>
27 #include <asm/mach/time.h>
28 #include <asm/hardware/cache-feroceon-l2.h>
29 #include <mach/kirkwood.h>
30 #include <mach/bridge-regs.h>
31 #include <linux/platform_data/asoc-kirkwood.h>
32 #include <linux/platform_data/mmc-mvsdio.h>
33 #include <linux/platform_data/mtd-orion_nand.h>
34 #include <linux/platform_data/usb-ehci-orion.h>
35 #include <plat/common.h>
36 #include <plat/time.h>
37 #include <linux/platform_data/dma-mv_xor.h>
38 #include "common.h"
39 #include "pm.h"
40
41 /* These can go away once Kirkwood uses the mvebu-mbus DT binding */
42 #define KIRKWOOD_MBUS_NAND_TARGET 0x01
43 #define KIRKWOOD_MBUS_NAND_ATTR 0x2f
44 #define KIRKWOOD_MBUS_SRAM_TARGET 0x03
45 #define KIRKWOOD_MBUS_SRAM_ATTR 0x01
46
47 /*****************************************************************************
48 * I/O Address Mapping
49 ****************************************************************************/
50 static struct map_desc kirkwood_io_desc[] __initdata = {
51 {
52 .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
53 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
54 .length = KIRKWOOD_REGS_SIZE,
55 .type = MT_DEVICE,
56 },
57 };
58
59 void __init kirkwood_map_io(void)
60 {
61 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
62 }
63
64 /*****************************************************************************
65 * CLK tree
66 ****************************************************************************/
67
68 static void enable_sata0(void)
69 {
70 /* Enable PLL and IVREF */
71 writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
72 /* Enable PHY */
73 writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
74 }
75
76 static void disable_sata0(void)
77 {
78 /* Disable PLL and IVREF */
79 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
80 /* Disable PHY */
81 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
82 }
83
84 static void enable_sata1(void)
85 {
86 /* Enable PLL and IVREF */
87 writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
88 /* Enable PHY */
89 writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
90 }
91
92 static void disable_sata1(void)
93 {
94 /* Disable PLL and IVREF */
95 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
96 /* Disable PHY */
97 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
98 }
99
100 static void disable_pcie0(void)
101 {
102 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
103 while (1)
104 if (readl(PCIE_STATUS) & 0x1)
105 break;
106 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
107 }
108
109 static void disable_pcie1(void)
110 {
111 u32 dev, rev;
112
113 kirkwood_pcie_id(&dev, &rev);
114
115 if (dev == MV88F6282_DEV_ID) {
116 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
117 while (1)
118 if (readl(PCIE1_STATUS) & 0x1)
119 break;
120 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
121 }
122 }
123
124 /* An extended version of the gated clk. This calls fn_en()/fn_dis
125 * before enabling/disabling the clock. We use this to turn on/off
126 * PHYs etc. */
127 struct clk_gate_fn {
128 struct clk_gate gate;
129 void (*fn_en)(void);
130 void (*fn_dis)(void);
131 };
132
133 #define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
134 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
135
136 static int clk_gate_fn_enable(struct clk_hw *hw)
137 {
138 struct clk_gate *gate = to_clk_gate(hw);
139 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
140 int ret;
141
142 ret = clk_gate_ops.enable(hw);
143 if (!ret && gate_fn->fn_en)
144 gate_fn->fn_en();
145
146 return ret;
147 }
148
149 static void clk_gate_fn_disable(struct clk_hw *hw)
150 {
151 struct clk_gate *gate = to_clk_gate(hw);
152 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
153
154 if (gate_fn->fn_dis)
155 gate_fn->fn_dis();
156
157 clk_gate_ops.disable(hw);
158 }
159
160 static struct clk_ops clk_gate_fn_ops;
161
162 static struct clk __init *clk_register_gate_fn(struct device *dev,
163 const char *name,
164 const char *parent_name, unsigned long flags,
165 void __iomem *reg, u8 bit_idx,
166 u8 clk_gate_flags, spinlock_t *lock,
167 void (*fn_en)(void), void (*fn_dis)(void))
168 {
169 struct clk_gate_fn *gate_fn;
170 struct clk *clk;
171 struct clk_init_data init;
172
173 gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
174 if (!gate_fn) {
175 pr_err("%s: could not allocate gated clk\n", __func__);
176 return ERR_PTR(-ENOMEM);
177 }
178
179 init.name = name;
180 init.ops = &clk_gate_fn_ops;
181 init.flags = flags;
182 init.parent_names = (parent_name ? &parent_name : NULL);
183 init.num_parents = (parent_name ? 1 : 0);
184
185 /* struct clk_gate assignments */
186 gate_fn->gate.reg = reg;
187 gate_fn->gate.bit_idx = bit_idx;
188 gate_fn->gate.flags = clk_gate_flags;
189 gate_fn->gate.lock = lock;
190 gate_fn->gate.hw.init = &init;
191 gate_fn->fn_en = fn_en;
192 gate_fn->fn_dis = fn_dis;
193
194 /* ops is the gate ops, but with our enable/disable functions */
195 if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
196 clk_gate_fn_ops.disable != clk_gate_fn_disable) {
197 clk_gate_fn_ops = clk_gate_ops;
198 clk_gate_fn_ops.enable = clk_gate_fn_enable;
199 clk_gate_fn_ops.disable = clk_gate_fn_disable;
200 }
201
202 clk = clk_register(dev, &gate_fn->gate.hw);
203
204 if (IS_ERR(clk))
205 kfree(gate_fn);
206
207 return clk;
208 }
209
210 static DEFINE_SPINLOCK(gating_lock);
211 static struct clk *tclk;
212
213 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
214 {
215 return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
216 bit_idx, 0, &gating_lock);
217 }
218
219 static struct clk __init *kirkwood_register_gate_fn(const char *name,
220 u8 bit_idx,
221 void (*fn_en)(void),
222 void (*fn_dis)(void))
223 {
224 return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
225 bit_idx, 0, &gating_lock, fn_en, fn_dis);
226 }
227
228 static struct clk *ge0, *ge1;
229
230 void __init kirkwood_clk_init(void)
231 {
232 struct clk *runit, *sata0, *sata1, *usb0, *sdio;
233 struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
234
235 tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
236 CLK_IS_ROOT, kirkwood_tclk);
237
238 runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
239 ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
240 ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
241 sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
242 enable_sata0, disable_sata0);
243 sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
244 enable_sata1, disable_sata1);
245 usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
246 sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
247 crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
248 xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
249 xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
250 pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
251 NULL, disable_pcie0);
252 pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
253 NULL, disable_pcie1);
254 audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
255 kirkwood_register_gate("tdm", CGC_BIT_TDM);
256 kirkwood_register_gate("tsu", CGC_BIT_TSU);
257
258 /* clkdev entries, mapping clks to devices */
259 orion_clkdev_add(NULL, "orion_spi.0", runit);
260 orion_clkdev_add(NULL, "orion_spi.1", runit);
261 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
262 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
263 orion_clkdev_add(NULL, "orion_wdt", tclk);
264 orion_clkdev_add("0", "sata_mv.0", sata0);
265 orion_clkdev_add("1", "sata_mv.0", sata1);
266 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
267 orion_clkdev_add(NULL, "orion_nand", runit);
268 orion_clkdev_add(NULL, "mvsdio", sdio);
269 orion_clkdev_add(NULL, "mv_crypto", crypto);
270 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
271 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
272 orion_clkdev_add("0", "pcie", pex0);
273 orion_clkdev_add("1", "pcie", pex1);
274 orion_clkdev_add(NULL, "mvebu-audio", audio);
275 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
276 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".1", runit);
277
278 /* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
279 * so should never be gated.
280 */
281 clk_prepare_enable(runit);
282 }
283
284 /*****************************************************************************
285 * EHCI0
286 ****************************************************************************/
287 void __init kirkwood_ehci_init(void)
288 {
289 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
290 }
291
292
293 /*****************************************************************************
294 * GE00
295 ****************************************************************************/
296 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
297 {
298 orion_ge00_init(eth_data,
299 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
300 IRQ_KIRKWOOD_GE00_ERR, 1600);
301 /* The interface forgets the MAC address assigned by u-boot if
302 the clock is turned off, so claim the clk now. */
303 clk_prepare_enable(ge0);
304 }
305
306
307 /*****************************************************************************
308 * GE01
309 ****************************************************************************/
310 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
311 {
312 orion_ge01_init(eth_data,
313 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
314 IRQ_KIRKWOOD_GE01_ERR, 1600);
315 clk_prepare_enable(ge1);
316 }
317
318
319 /*****************************************************************************
320 * Ethernet switch
321 ****************************************************************************/
322 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
323 {
324 orion_ge00_switch_init(d, irq);
325 }
326
327
328 /*****************************************************************************
329 * NAND flash
330 ****************************************************************************/
331 static struct resource kirkwood_nand_resource = {
332 .flags = IORESOURCE_MEM,
333 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
334 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
335 KIRKWOOD_NAND_MEM_SIZE - 1,
336 };
337
338 static struct orion_nand_data kirkwood_nand_data = {
339 .cle = 0,
340 .ale = 1,
341 .width = 8,
342 };
343
344 static struct platform_device kirkwood_nand_flash = {
345 .name = "orion_nand",
346 .id = -1,
347 .dev = {
348 .platform_data = &kirkwood_nand_data,
349 },
350 .resource = &kirkwood_nand_resource,
351 .num_resources = 1,
352 };
353
354 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
355 int chip_delay)
356 {
357 kirkwood_nand_data.parts = parts;
358 kirkwood_nand_data.nr_parts = nr_parts;
359 kirkwood_nand_data.chip_delay = chip_delay;
360 platform_device_register(&kirkwood_nand_flash);
361 }
362
363 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
364 int (*dev_ready)(struct mtd_info *))
365 {
366 kirkwood_nand_data.parts = parts;
367 kirkwood_nand_data.nr_parts = nr_parts;
368 kirkwood_nand_data.dev_ready = dev_ready;
369 platform_device_register(&kirkwood_nand_flash);
370 }
371
372 /*****************************************************************************
373 * SoC RTC
374 ****************************************************************************/
375 static void __init kirkwood_rtc_init(void)
376 {
377 orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
378 }
379
380
381 /*****************************************************************************
382 * SATA
383 ****************************************************************************/
384 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
385 {
386 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
387 }
388
389
390 /*****************************************************************************
391 * SD/SDIO/MMC
392 ****************************************************************************/
393 static struct resource mvsdio_resources[] = {
394 [0] = {
395 .start = SDIO_PHYS_BASE,
396 .end = SDIO_PHYS_BASE + SZ_1K - 1,
397 .flags = IORESOURCE_MEM,
398 },
399 [1] = {
400 .start = IRQ_KIRKWOOD_SDIO,
401 .end = IRQ_KIRKWOOD_SDIO,
402 .flags = IORESOURCE_IRQ,
403 },
404 };
405
406 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
407
408 static struct platform_device kirkwood_sdio = {
409 .name = "mvsdio",
410 .id = -1,
411 .dev = {
412 .dma_mask = &mvsdio_dmamask,
413 .coherent_dma_mask = DMA_BIT_MASK(32),
414 },
415 .num_resources = ARRAY_SIZE(mvsdio_resources),
416 .resource = mvsdio_resources,
417 };
418
419 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
420 {
421 u32 dev, rev;
422
423 kirkwood_pcie_id(&dev, &rev);
424 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
425 mvsdio_data->clock = 100000000;
426 else
427 mvsdio_data->clock = 200000000;
428 kirkwood_sdio.dev.platform_data = mvsdio_data;
429 platform_device_register(&kirkwood_sdio);
430 }
431
432
433 /*****************************************************************************
434 * SPI
435 ****************************************************************************/
436 void __init kirkwood_spi_init(void)
437 {
438 orion_spi_init(SPI_PHYS_BASE);
439 }
440
441
442 /*****************************************************************************
443 * I2C
444 ****************************************************************************/
445 void __init kirkwood_i2c_init(void)
446 {
447 orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
448 }
449
450
451 /*****************************************************************************
452 * UART0
453 ****************************************************************************/
454
455 void __init kirkwood_uart0_init(void)
456 {
457 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
458 IRQ_KIRKWOOD_UART_0, tclk);
459 }
460
461
462 /*****************************************************************************
463 * UART1
464 ****************************************************************************/
465 void __init kirkwood_uart1_init(void)
466 {
467 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
468 IRQ_KIRKWOOD_UART_1, tclk);
469 }
470
471 /*****************************************************************************
472 * Cryptographic Engines and Security Accelerator (CESA)
473 ****************************************************************************/
474 void __init kirkwood_crypto_init(void)
475 {
476 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
477 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
478 }
479
480
481 /*****************************************************************************
482 * XOR0
483 ****************************************************************************/
484 void __init kirkwood_xor0_init(void)
485 {
486 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
487 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
488 }
489
490
491 /*****************************************************************************
492 * XOR1
493 ****************************************************************************/
494 void __init kirkwood_xor1_init(void)
495 {
496 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
497 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
498 }
499
500
501 /*****************************************************************************
502 * Watchdog
503 ****************************************************************************/
504 void __init kirkwood_wdt_init(void)
505 {
506 orion_wdt_init();
507 }
508
509 /*****************************************************************************
510 * CPU idle
511 ****************************************************************************/
512 static struct resource kirkwood_cpuidle_resource[] = {
513 {
514 .flags = IORESOURCE_MEM,
515 .start = DDR_OPERATION_BASE,
516 .end = DDR_OPERATION_BASE + 3,
517 },
518 };
519
520 static struct platform_device kirkwood_cpuidle = {
521 .name = "kirkwood_cpuidle",
522 .id = -1,
523 .resource = kirkwood_cpuidle_resource,
524 .num_resources = 1,
525 };
526
527 void __init kirkwood_cpuidle_init(void)
528 {
529 platform_device_register(&kirkwood_cpuidle);
530 }
531
532 /*****************************************************************************
533 * Time handling
534 ****************************************************************************/
535 void __init kirkwood_init_early(void)
536 {
537 orion_time_set_base(TIMER_VIRT_BASE);
538 }
539
540 int kirkwood_tclk;
541
542 static int __init kirkwood_find_tclk(void)
543 {
544 u32 dev, rev;
545
546 kirkwood_pcie_id(&dev, &rev);
547
548 if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
549 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
550 return 200000000;
551
552 return 166666667;
553 }
554
555 void __init kirkwood_timer_init(void)
556 {
557 kirkwood_tclk = kirkwood_find_tclk();
558
559 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
560 IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
561 }
562
563 /*****************************************************************************
564 * Audio
565 ****************************************************************************/
566 static struct resource kirkwood_audio_resources[] = {
567 [0] = {
568 .start = AUDIO_PHYS_BASE,
569 .end = AUDIO_PHYS_BASE + SZ_16K - 1,
570 .flags = IORESOURCE_MEM,
571 },
572 [1] = {
573 .start = IRQ_KIRKWOOD_I2S,
574 .end = IRQ_KIRKWOOD_I2S,
575 .flags = IORESOURCE_IRQ,
576 },
577 };
578
579 static struct kirkwood_asoc_platform_data kirkwood_audio_data = {
580 .burst = 128,
581 };
582
583 static struct platform_device kirkwood_audio_device = {
584 .name = "mvebu-audio",
585 .id = -1,
586 .num_resources = ARRAY_SIZE(kirkwood_audio_resources),
587 .resource = kirkwood_audio_resources,
588 .dev = {
589 .platform_data = &kirkwood_audio_data,
590 },
591 };
592
593 void __init kirkwood_audio_init(void)
594 {
595 platform_device_register(&kirkwood_audio_device);
596 }
597
598 /*****************************************************************************
599 * CPU Frequency
600 ****************************************************************************/
601 static struct resource kirkwood_cpufreq_resources[] = {
602 [0] = {
603 .start = CPU_CONTROL_PHYS,
604 .end = CPU_CONTROL_PHYS + 3,
605 .flags = IORESOURCE_MEM,
606 },
607 };
608
609 static struct platform_device kirkwood_cpufreq_device = {
610 .name = "kirkwood-cpufreq",
611 .id = -1,
612 .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources),
613 .resource = kirkwood_cpufreq_resources,
614 };
615
616 void __init kirkwood_cpufreq_init(void)
617 {
618 platform_device_register(&kirkwood_cpufreq_device);
619 }
620
621 /*****************************************************************************
622 * General
623 ****************************************************************************/
624 /*
625 * Identify device ID and revision.
626 */
627 char * __init kirkwood_id(void)
628 {
629 u32 dev, rev;
630
631 kirkwood_pcie_id(&dev, &rev);
632
633 if (dev == MV88F6281_DEV_ID) {
634 if (rev == MV88F6281_REV_Z0)
635 return "MV88F6281-Z0";
636 else if (rev == MV88F6281_REV_A0)
637 return "MV88F6281-A0";
638 else if (rev == MV88F6281_REV_A1)
639 return "MV88F6281-A1";
640 else
641 return "MV88F6281-Rev-Unsupported";
642 } else if (dev == MV88F6192_DEV_ID) {
643 if (rev == MV88F6192_REV_Z0)
644 return "MV88F6192-Z0";
645 else if (rev == MV88F6192_REV_A0)
646 return "MV88F6192-A0";
647 else if (rev == MV88F6192_REV_A1)
648 return "MV88F6192-A1";
649 else
650 return "MV88F6192-Rev-Unsupported";
651 } else if (dev == MV88F6180_DEV_ID) {
652 if (rev == MV88F6180_REV_A0)
653 return "MV88F6180-Rev-A0";
654 else if (rev == MV88F6180_REV_A1)
655 return "MV88F6180-Rev-A1";
656 else
657 return "MV88F6180-Rev-Unsupported";
658 } else if (dev == MV88F6282_DEV_ID) {
659 if (rev == MV88F6282_REV_A0)
660 return "MV88F6282-Rev-A0";
661 else if (rev == MV88F6282_REV_A1)
662 return "MV88F6282-Rev-A1";
663 else
664 return "MV88F6282-Rev-Unsupported";
665 } else {
666 return "Device-Unknown";
667 }
668 }
669
670 void __init kirkwood_setup_wins(void)
671 {
672 mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
673 KIRKWOOD_MBUS_NAND_ATTR,
674 KIRKWOOD_NAND_MEM_PHYS_BASE,
675 KIRKWOOD_NAND_MEM_SIZE);
676 mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
677 KIRKWOOD_MBUS_SRAM_ATTR,
678 KIRKWOOD_SRAM_PHYS_BASE,
679 KIRKWOOD_SRAM_SIZE);
680 }
681
682 void __init kirkwood_l2_init(void)
683 {
684 #ifdef CONFIG_CACHE_FEROCEON_L2
685 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
686 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
687 feroceon_l2_init(1);
688 #else
689 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
690 feroceon_l2_init(0);
691 #endif
692 #endif
693 }
694
695 void __init kirkwood_init(void)
696 {
697 pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
698
699 /*
700 * Disable propagation of mbus errors to the CPU local bus,
701 * as this causes mbus errors (which can occur for example
702 * for PCI aborts) to throw CPU aborts, which we're not set
703 * up to deal with.
704 */
705 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
706
707 BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
708 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
709 DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
710
711 kirkwood_setup_wins();
712
713 kirkwood_l2_init();
714
715 /* Setup root of clk tree */
716 kirkwood_clk_init();
717
718 /* internal devices that every board has */
719 kirkwood_rtc_init();
720 kirkwood_wdt_init();
721 kirkwood_xor0_init();
722 kirkwood_xor1_init();
723 kirkwood_crypto_init();
724
725 kirkwood_pm_init();
726 kirkwood_cpuidle_init();
727 #ifdef CONFIG_KEXEC
728 kexec_reinit = kirkwood_enable_pcie;
729 #endif
730 }
731
732 void kirkwood_restart(enum reboot_mode mode, const char *cmd)
733 {
734 /*
735 * Enable soft reset to assert RSTOUTn.
736 */
737 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
738
739 /*
740 * Assert soft reset.
741 */
742 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
743
744 while (1)
745 ;
746 }
Linux kernel - Deliverables
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