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Merge branch 'lpc32xx/fixup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[deliverable/linux.git] / arch / arm / mach-lpc32xx / clock.c
1 /*
2 * arch/arm/mach-lpc32xx/clock.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * LPC32xx clock management driver overview
21 *
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
29 *
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
35 * disabled normally.
36 * 32KHz oscillator*
37 * / | \
38 * RTC* PLL397^ TOUCH
39 * /
40 * Main oscillator^ /
41 * | \ /
42 * | SYSCLK&
43 * | \
44 * | \
45 * USB_PLL HCLK_PLL&
46 * | | |
47 * USB host/device PCLK& |
48 * | |
49 * Peripherals
50 *
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
59 *
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
67 *
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
76 * to an external pin.
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
78 * this driver.
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
83 */
84
85 #include <linux/export.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/errno.h>
89 #include <linux/device.h>
90 #include <linux/err.h>
91 #include <linux/clk.h>
92 #include <linux/amba/bus.h>
93 #include <linux/amba/clcd.h>
94 #include <linux/clkdev.h>
95
96 #include <mach/hardware.h>
97 #include <mach/platform.h>
98 #include "clock.h"
99 #include "common.h"
100
101 static DEFINE_SPINLOCK(global_clkregs_lock);
102
103 static struct clk clk_armpll;
104 static struct clk clk_usbpll;
105
106 /*
107 * Post divider values for PLLs based on selected register value
108 */
109 static const u32 pll_postdivs[4] = {1, 2, 4, 8};
110
111 static unsigned long local_return_parent_rate(struct clk *clk)
112 {
113 /*
114 * If a clock has a rate of 0, then it inherits it's parent
115 * clock rate
116 */
117 while (clk->rate == 0)
118 clk = clk->parent;
119
120 return clk->rate;
121 }
122
123 /* 32KHz clock has a fixed rate and is not stoppable */
124 static struct clk osc_32KHz = {
125 .rate = LPC32XX_CLOCK_OSC_FREQ,
126 .get_rate = local_return_parent_rate,
127 };
128
129 static int local_pll397_enable(struct clk *clk, int enable)
130 {
131 u32 reg;
132 unsigned long timeout = jiffies + msecs_to_jiffies(10);
133
134 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
135
136 if (enable == 0) {
137 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
138 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
139 } else {
140 /* Enable PLL397 */
141 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
142 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
143
144 /* Wait for PLL397 lock */
145 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
146 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
147 time_before(jiffies, timeout))
148 cpu_relax();
149
150 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
151 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
152 return -ENODEV;
153 }
154
155 return 0;
156 }
157
158 static int local_oscmain_enable(struct clk *clk, int enable)
159 {
160 u32 reg;
161 unsigned long timeout = jiffies + msecs_to_jiffies(10);
162
163 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
164
165 if (enable == 0) {
166 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
167 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
168 } else {
169 /* Enable main oscillator */
170 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
171 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
172
173 /* Wait for main oscillator to start */
174 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
175 LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
176 time_before(jiffies, timeout))
177 cpu_relax();
178
179 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
180 LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
181 return -ENODEV;
182 }
183
184 return 0;
185 }
186
187 static struct clk osc_pll397 = {
188 .parent = &osc_32KHz,
189 .enable = local_pll397_enable,
190 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
191 .get_rate = local_return_parent_rate,
192 };
193
194 static struct clk osc_main = {
195 .enable = local_oscmain_enable,
196 .rate = LPC32XX_MAIN_OSC_FREQ,
197 .get_rate = local_return_parent_rate,
198 };
199
200 static struct clk clk_sys;
201
202 /*
203 * Convert a PLL register value to a PLL output frequency
204 */
205 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
206 {
207 struct clk_pll_setup pllcfg;
208
209 pllcfg.cco_bypass_b15 = 0;
210 pllcfg.direct_output_b14 = 0;
211 pllcfg.fdbk_div_ctrl_b13 = 0;
212 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
213 pllcfg.cco_bypass_b15 = 1;
214 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
215 pllcfg.direct_output_b14 = 1;
216 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
217 pllcfg.fdbk_div_ctrl_b13 = 1;
218 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
219 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
220 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
221
222 return clk_check_pll_setup(inputclk, &pllcfg);
223 }
224
225 /*
226 * Setup the HCLK PLL with a PLL structure
227 */
228 static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
229 {
230 u32 tv, tmp = 0;
231
232 if (PllSetup->analog_on != 0)
233 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
234 if (PllSetup->cco_bypass_b15 != 0)
235 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
236 if (PllSetup->direct_output_b14 != 0)
237 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
238 if (PllSetup->fdbk_div_ctrl_b13 != 0)
239 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
240
241 tv = ffs(PllSetup->pll_p) - 1;
242 if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
243 return 0;
244
245 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
246 tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
247 tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
248
249 return tmp;
250 }
251
252 /*
253 * Update the ARM core PLL frequency rate variable from the actual PLL setting
254 */
255 static void local_update_armpll_rate(void)
256 {
257 u32 clkin, pllreg;
258
259 clkin = clk_armpll.parent->rate;
260 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
261
262 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
263 }
264
265 /*
266 * Find a PLL configuration for the selected input frequency
267 */
268 static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
269 struct clk_pll_setup *pllsetup)
270 {
271 u32 ifreq, freqtol, m, n, p, fclkout;
272
273 /* Determine frequency tolerance limits */
274 freqtol = target_freq / 250;
275 ifreq = pllin_freq;
276
277 /* Is direct bypass mode possible? */
278 if (abs(pllin_freq - target_freq) <= freqtol) {
279 pllsetup->analog_on = 0;
280 pllsetup->cco_bypass_b15 = 1;
281 pllsetup->direct_output_b14 = 1;
282 pllsetup->fdbk_div_ctrl_b13 = 1;
283 pllsetup->pll_p = pll_postdivs[0];
284 pllsetup->pll_n = 1;
285 pllsetup->pll_m = 1;
286 return clk_check_pll_setup(ifreq, pllsetup);
287 } else if (target_freq <= ifreq) {
288 pllsetup->analog_on = 0;
289 pllsetup->cco_bypass_b15 = 1;
290 pllsetup->direct_output_b14 = 0;
291 pllsetup->fdbk_div_ctrl_b13 = 1;
292 pllsetup->pll_n = 1;
293 pllsetup->pll_m = 1;
294 for (p = 0; p <= 3; p++) {
295 pllsetup->pll_p = pll_postdivs[p];
296 fclkout = clk_check_pll_setup(ifreq, pllsetup);
297 if (abs(target_freq - fclkout) <= freqtol)
298 return fclkout;
299 }
300 }
301
302 /* Is direct mode possible? */
303 pllsetup->analog_on = 1;
304 pllsetup->cco_bypass_b15 = 0;
305 pllsetup->direct_output_b14 = 1;
306 pllsetup->fdbk_div_ctrl_b13 = 0;
307 pllsetup->pll_p = pll_postdivs[0];
308 for (m = 1; m <= 256; m++) {
309 for (n = 1; n <= 4; n++) {
310 /* Compute output frequency for this value */
311 pllsetup->pll_n = n;
312 pllsetup->pll_m = m;
313 fclkout = clk_check_pll_setup(ifreq,
314 pllsetup);
315 if (abs(target_freq - fclkout) <=
316 freqtol)
317 return fclkout;
318 }
319 }
320
321 /* Is integer mode possible? */
322 pllsetup->analog_on = 1;
323 pllsetup->cco_bypass_b15 = 0;
324 pllsetup->direct_output_b14 = 0;
325 pllsetup->fdbk_div_ctrl_b13 = 1;
326 for (m = 1; m <= 256; m++) {
327 for (n = 1; n <= 4; n++) {
328 for (p = 0; p < 4; p++) {
329 /* Compute output frequency */
330 pllsetup->pll_p = pll_postdivs[p];
331 pllsetup->pll_n = n;
332 pllsetup->pll_m = m;
333 fclkout = clk_check_pll_setup(
334 ifreq, pllsetup);
335 if (abs(target_freq - fclkout) <= freqtol)
336 return fclkout;
337 }
338 }
339 }
340
341 /* Try non-integer mode */
342 pllsetup->analog_on = 1;
343 pllsetup->cco_bypass_b15 = 0;
344 pllsetup->direct_output_b14 = 0;
345 pllsetup->fdbk_div_ctrl_b13 = 0;
346 for (m = 1; m <= 256; m++) {
347 for (n = 1; n <= 4; n++) {
348 for (p = 0; p < 4; p++) {
349 /* Compute output frequency */
350 pllsetup->pll_p = pll_postdivs[p];
351 pllsetup->pll_n = n;
352 pllsetup->pll_m = m;
353 fclkout = clk_check_pll_setup(
354 ifreq, pllsetup);
355 if (abs(target_freq - fclkout) <= freqtol)
356 return fclkout;
357 }
358 }
359 }
360
361 return 0;
362 }
363
364 static struct clk clk_armpll = {
365 .parent = &clk_sys,
366 .get_rate = local_return_parent_rate,
367 };
368
369 /*
370 * Setup the USB PLL with a PLL structure
371 */
372 static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
373 {
374 u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
375
376 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
377 reg |= tmp;
378 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
379
380 return clk_check_pll_setup(clk_usbpll.parent->rate,
381 pHCLKPllSetup);
382 }
383
384 static int local_usbpll_enable(struct clk *clk, int enable)
385 {
386 u32 reg;
387 int ret = -ENODEV;
388 unsigned long timeout = jiffies + msecs_to_jiffies(10);
389
390 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
391
392 if (enable == 0) {
393 reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
394 LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
395 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
396 } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
397 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
398 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
399
400 /* Wait for PLL lock */
401 while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
402 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
403 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
404 ret = 0;
405 }
406
407 if (ret == 0) {
408 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
409 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
410 }
411 }
412
413 return ret;
414 }
415
416 static unsigned long local_usbpll_round_rate(struct clk *clk,
417 unsigned long rate)
418 {
419 u32 clkin, usbdiv;
420 struct clk_pll_setup pllsetup;
421
422 /*
423 * Unlike other clocks, this clock has a KHz input rate, so bump
424 * it up to work with the PLL function
425 */
426 rate = rate * 1000;
427
428 clkin = clk->parent->rate;
429 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
430 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
431 clkin = clkin / usbdiv;
432
433 /* Try to find a good rate setup */
434 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
435 return 0;
436
437 return clk_check_pll_setup(clkin, &pllsetup);
438 }
439
440 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
441 {
442 u32 clkin, reg, usbdiv;
443 struct clk_pll_setup pllsetup;
444
445 /*
446 * Unlike other clocks, this clock has a KHz input rate, so bump
447 * it up to work with the PLL function
448 */
449 rate = rate * 1000;
450
451 clkin = clk->get_rate(clk);
452 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
453 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
454 clkin = clkin / usbdiv;
455
456 /* Try to find a good rate setup */
457 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
458 return -EINVAL;
459
460 local_usbpll_enable(clk, 0);
461
462 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
463 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
464 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
465
466 pllsetup.analog_on = 1;
467 local_clk_usbpll_setup(&pllsetup);
468
469 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
470
471 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
472 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
473 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
474
475 return 0;
476 }
477
478 static struct clk clk_usbpll = {
479 .parent = &osc_main,
480 .set_rate = local_usbpll_set_rate,
481 .enable = local_usbpll_enable,
482 .rate = 48000, /* In KHz */
483 .get_rate = local_return_parent_rate,
484 .round_rate = local_usbpll_round_rate,
485 };
486
487 static u32 clk_get_hclk_div(void)
488 {
489 static const u32 hclkdivs[4] = {1, 2, 4, 4};
490 return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
491 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
492 }
493
494 static struct clk clk_hclk = {
495 .parent = &clk_armpll,
496 .get_rate = local_return_parent_rate,
497 };
498
499 static struct clk clk_pclk = {
500 .parent = &clk_armpll,
501 .get_rate = local_return_parent_rate,
502 };
503
504 static int local_onoff_enable(struct clk *clk, int enable)
505 {
506 u32 tmp;
507
508 tmp = __raw_readl(clk->enable_reg);
509
510 if (enable == 0)
511 tmp &= ~clk->enable_mask;
512 else
513 tmp |= clk->enable_mask;
514
515 __raw_writel(tmp, clk->enable_reg);
516
517 return 0;
518 }
519
520 /* Peripheral clock sources */
521 static struct clk clk_timer0 = {
522 .parent = &clk_pclk,
523 .enable = local_onoff_enable,
524 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
525 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
526 .get_rate = local_return_parent_rate,
527 };
528 static struct clk clk_timer1 = {
529 .parent = &clk_pclk,
530 .enable = local_onoff_enable,
531 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
532 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
533 .get_rate = local_return_parent_rate,
534 };
535 static struct clk clk_timer2 = {
536 .parent = &clk_pclk,
537 .enable = local_onoff_enable,
538 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
539 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
540 .get_rate = local_return_parent_rate,
541 };
542 static struct clk clk_timer3 = {
543 .parent = &clk_pclk,
544 .enable = local_onoff_enable,
545 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
546 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
547 .get_rate = local_return_parent_rate,
548 };
549 static struct clk clk_wdt = {
550 .parent = &clk_pclk,
551 .enable = local_onoff_enable,
552 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
553 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
554 .get_rate = local_return_parent_rate,
555 };
556 static struct clk clk_vfp9 = {
557 .parent = &clk_pclk,
558 .enable = local_onoff_enable,
559 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
560 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
561 .get_rate = local_return_parent_rate,
562 };
563 static struct clk clk_dma = {
564 .parent = &clk_hclk,
565 .enable = local_onoff_enable,
566 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
567 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
568 .get_rate = local_return_parent_rate,
569 };
570
571 static struct clk clk_uart3 = {
572 .parent = &clk_pclk,
573 .enable = local_onoff_enable,
574 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
575 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
576 .get_rate = local_return_parent_rate,
577 };
578
579 static struct clk clk_uart4 = {
580 .parent = &clk_pclk,
581 .enable = local_onoff_enable,
582 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
583 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
584 .get_rate = local_return_parent_rate,
585 };
586
587 static struct clk clk_uart5 = {
588 .parent = &clk_pclk,
589 .enable = local_onoff_enable,
590 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
591 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
592 .get_rate = local_return_parent_rate,
593 };
594
595 static struct clk clk_uart6 = {
596 .parent = &clk_pclk,
597 .enable = local_onoff_enable,
598 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
599 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
600 .get_rate = local_return_parent_rate,
601 };
602
603 static struct clk clk_i2c0 = {
604 .parent = &clk_hclk,
605 .enable = local_onoff_enable,
606 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
607 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
608 .get_rate = local_return_parent_rate,
609 };
610
611 static struct clk clk_i2c1 = {
612 .parent = &clk_hclk,
613 .enable = local_onoff_enable,
614 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
615 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
616 .get_rate = local_return_parent_rate,
617 };
618
619 static struct clk clk_i2c2 = {
620 .parent = &clk_pclk,
621 .enable = local_onoff_enable,
622 .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
623 .enable_mask = 0x4,
624 .get_rate = local_return_parent_rate,
625 };
626
627 static struct clk clk_ssp0 = {
628 .parent = &clk_hclk,
629 .enable = local_onoff_enable,
630 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
631 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
632 .get_rate = local_return_parent_rate,
633 };
634
635 static struct clk clk_ssp1 = {
636 .parent = &clk_hclk,
637 .enable = local_onoff_enable,
638 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
639 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
640 .get_rate = local_return_parent_rate,
641 };
642
643 static struct clk clk_kscan = {
644 .parent = &osc_32KHz,
645 .enable = local_onoff_enable,
646 .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
647 .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
648 .get_rate = local_return_parent_rate,
649 };
650
651 static struct clk clk_nand = {
652 .parent = &clk_hclk,
653 .enable = local_onoff_enable,
654 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
655 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
656 .get_rate = local_return_parent_rate,
657 };
658
659 static struct clk clk_i2s0 = {
660 .parent = &clk_hclk,
661 .enable = local_onoff_enable,
662 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
663 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
664 .get_rate = local_return_parent_rate,
665 };
666
667 static struct clk clk_i2s1 = {
668 .parent = &clk_hclk,
669 .enable = local_onoff_enable,
670 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
671 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
672 .get_rate = local_return_parent_rate,
673 };
674
675 static struct clk clk_net = {
676 .parent = &clk_hclk,
677 .enable = local_onoff_enable,
678 .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
679 .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
680 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
681 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
682 .get_rate = local_return_parent_rate,
683 };
684
685 static struct clk clk_rtc = {
686 .parent = &osc_32KHz,
687 .rate = 1, /* 1 Hz */
688 .get_rate = local_return_parent_rate,
689 };
690
691 static struct clk clk_usbd = {
692 .parent = &clk_usbpll,
693 .enable = local_onoff_enable,
694 .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
695 .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
696 .get_rate = local_return_parent_rate,
697 };
698
699 static int tsc_onoff_enable(struct clk *clk, int enable)
700 {
701 u32 tmp;
702
703 /* Make sure 32KHz clock is the selected clock */
704 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
705 tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
706 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
707
708 if (enable == 0)
709 __raw_writel(0, clk->enable_reg);
710 else
711 __raw_writel(clk->enable_mask, clk->enable_reg);
712
713 return 0;
714 }
715
716 static struct clk clk_tsc = {
717 .parent = &osc_32KHz,
718 .enable = tsc_onoff_enable,
719 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
720 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
721 .get_rate = local_return_parent_rate,
722 };
723
724 static int mmc_onoff_enable(struct clk *clk, int enable)
725 {
726 u32 tmp;
727
728 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
729 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
730
731 /* If rate is 0, disable clock */
732 if (enable != 0)
733 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
734
735 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
736
737 return 0;
738 }
739
740 static unsigned long mmc_get_rate(struct clk *clk)
741 {
742 u32 div, rate, oldclk;
743
744 /* The MMC clock must be on when accessing an MMC register */
745 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
746 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
747 LPC32XX_CLKPWR_MS_CTRL);
748 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
749 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
750
751 /* Get the parent clock rate */
752 rate = clk->parent->get_rate(clk->parent);
753
754 /* Get the MMC controller clock divider value */
755 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
756
757 if (!div)
758 div = 1;
759
760 return rate / div;
761 }
762
763 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
764 {
765 unsigned long div, prate;
766
767 /* Get the parent clock rate */
768 prate = clk->parent->get_rate(clk->parent);
769
770 if (rate >= prate)
771 return prate;
772
773 div = prate / rate;
774 if (div > 0xf)
775 div = 0xf;
776
777 return prate / div;
778 }
779
780 static int mmc_set_rate(struct clk *clk, unsigned long rate)
781 {
782 u32 oldclk, tmp;
783 unsigned long prate, div, crate = mmc_round_rate(clk, rate);
784
785 prate = clk->parent->get_rate(clk->parent);
786
787 div = prate / crate;
788
789 /* The MMC clock must be on when accessing an MMC register */
790 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
791 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
792 LPC32XX_CLKPWR_MS_CTRL);
793 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
794 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
795 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
796 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
797
798 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
799
800 return 0;
801 }
802
803 static struct clk clk_mmc = {
804 .parent = &clk_armpll,
805 .set_rate = mmc_set_rate,
806 .get_rate = mmc_get_rate,
807 .round_rate = mmc_round_rate,
808 .enable = mmc_onoff_enable,
809 .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
810 .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
811 };
812
813 static unsigned long clcd_get_rate(struct clk *clk)
814 {
815 u32 tmp, div, rate, oldclk;
816
817 /* The LCD clock must be on when accessing an LCD register */
818 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
819 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
820 LPC32XX_CLKPWR_LCDCLK_CTRL);
821 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
822 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
823
824 rate = clk->parent->get_rate(clk->parent);
825
826 /* Only supports internal clocking */
827 if (tmp & TIM2_BCD)
828 return rate;
829
830 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
831 tmp = rate / (2 + div);
832
833 return tmp;
834 }
835
836 static int clcd_set_rate(struct clk *clk, unsigned long rate)
837 {
838 u32 tmp, prate, div, oldclk;
839
840 /* The LCD clock must be on when accessing an LCD register */
841 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
842 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
843 LPC32XX_CLKPWR_LCDCLK_CTRL);
844
845 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
846 prate = clk->parent->get_rate(clk->parent);
847
848 if (rate < prate) {
849 /* Find closest divider */
850 div = prate / rate;
851 if (div >= 2) {
852 div -= 2;
853 tmp &= ~TIM2_BCD;
854 }
855
856 tmp &= ~(0xF800001F);
857 tmp |= (div & 0x1F);
858 tmp |= (((div >> 5) & 0x1F) << 27);
859 }
860
861 __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
862 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
863
864 return 0;
865 }
866
867 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
868 {
869 u32 prate, div;
870
871 prate = clk->parent->get_rate(clk->parent);
872
873 if (rate >= prate)
874 rate = prate;
875 else {
876 div = prate / rate;
877 if (div > 0x3ff)
878 div = 0x3ff;
879
880 rate = prate / div;
881 }
882
883 return rate;
884 }
885
886 static struct clk clk_lcd = {
887 .parent = &clk_hclk,
888 .set_rate = clcd_set_rate,
889 .get_rate = clcd_get_rate,
890 .round_rate = clcd_round_rate,
891 .enable = local_onoff_enable,
892 .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
893 .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
894 };
895
896 static void local_clk_disable(struct clk *clk)
897 {
898 /* Don't attempt to disable clock if it has no users */
899 if (clk->usecount > 0) {
900 clk->usecount--;
901
902 /* Only disable clock when it has no more users */
903 if ((clk->usecount == 0) && (clk->enable))
904 clk->enable(clk, 0);
905
906 /* Check parent clocks, they may need to be disabled too */
907 if (clk->parent)
908 local_clk_disable(clk->parent);
909 }
910 }
911
912 static int local_clk_enable(struct clk *clk)
913 {
914 int ret = 0;
915
916 /* Enable parent clocks first and update use counts */
917 if (clk->parent)
918 ret = local_clk_enable(clk->parent);
919
920 if (!ret) {
921 /* Only enable clock if it's currently disabled */
922 if ((clk->usecount == 0) && (clk->enable))
923 ret = clk->enable(clk, 1);
924
925 if (!ret)
926 clk->usecount++;
927 else if (clk->parent)
928 local_clk_disable(clk->parent);
929 }
930
931 return ret;
932 }
933
934 /*
935 * clk_enable - inform the system when the clock source should be running.
936 */
937 int clk_enable(struct clk *clk)
938 {
939 int ret;
940 unsigned long flags;
941
942 spin_lock_irqsave(&global_clkregs_lock, flags);
943 ret = local_clk_enable(clk);
944 spin_unlock_irqrestore(&global_clkregs_lock, flags);
945
946 return ret;
947 }
948 EXPORT_SYMBOL(clk_enable);
949
950 /*
951 * clk_disable - inform the system when the clock source is no longer required
952 */
953 void clk_disable(struct clk *clk)
954 {
955 unsigned long flags;
956
957 spin_lock_irqsave(&global_clkregs_lock, flags);
958 local_clk_disable(clk);
959 spin_unlock_irqrestore(&global_clkregs_lock, flags);
960 }
961 EXPORT_SYMBOL(clk_disable);
962
963 /*
964 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
965 */
966 unsigned long clk_get_rate(struct clk *clk)
967 {
968 return clk->get_rate(clk);
969 }
970 EXPORT_SYMBOL(clk_get_rate);
971
972 /*
973 * clk_set_rate - set the clock rate for a clock source
974 */
975 int clk_set_rate(struct clk *clk, unsigned long rate)
976 {
977 int ret = -EINVAL;
978
979 /*
980 * Most system clocks can only be enabled or disabled, with
981 * the actual rate set as part of the peripheral dividers
982 * instead of high level clock control
983 */
984 if (clk->set_rate)
985 ret = clk->set_rate(clk, rate);
986
987 return ret;
988 }
989 EXPORT_SYMBOL(clk_set_rate);
990
991 /*
992 * clk_round_rate - adjust a rate to the exact rate a clock can provide
993 */
994 long clk_round_rate(struct clk *clk, unsigned long rate)
995 {
996 if (clk->round_rate)
997 rate = clk->round_rate(clk, rate);
998 else
999 rate = clk->get_rate(clk);
1000
1001 return rate;
1002 }
1003 EXPORT_SYMBOL(clk_round_rate);
1004
1005 /*
1006 * clk_set_parent - set the parent clock source for this clock
1007 */
1008 int clk_set_parent(struct clk *clk, struct clk *parent)
1009 {
1010 /* Clock re-parenting is not supported */
1011 return -EINVAL;
1012 }
1013 EXPORT_SYMBOL(clk_set_parent);
1014
1015 /*
1016 * clk_get_parent - get the parent clock source for this clock
1017 */
1018 struct clk *clk_get_parent(struct clk *clk)
1019 {
1020 return clk->parent;
1021 }
1022 EXPORT_SYMBOL(clk_get_parent);
1023
1024 #define _REGISTER_CLOCK(d, n, c) \
1025 { \
1026 .dev_id = (d), \
1027 .con_id = (n), \
1028 .clk = &(c), \
1029 },
1030
1031 static struct clk_lookup lookups[] = {
1032 _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
1033 _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
1034 _REGISTER_CLOCK(NULL, "osc_main", osc_main)
1035 _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
1036 _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
1037 _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
1038 _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
1039 _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
1040 _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
1041 _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
1042 _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
1043 _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
1044 _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
1045 _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
1046 _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
1047 _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
1048 _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
1049 _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
1050 _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
1051 _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
1052 _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
1053 _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
1054 _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
1055 _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
1056 _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
1057 _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
1058 _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
1059 _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
1060 _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
1061 _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
1062 _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
1063 _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
1064 _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
1065 _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
1066 };
1067
1068 static int __init clk_init(void)
1069 {
1070 int i;
1071
1072 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1073 clkdev_add(&lookups[i]);
1074
1075 /*
1076 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1077 * parent clock used for the ARM PLL and is used to derive
1078 * the many system clock rates in the device.
1079 */
1080 if (clk_is_sysclk_mainosc() != 0)
1081 clk_sys.parent = &osc_main;
1082 else
1083 clk_sys.parent = &osc_pll397;
1084
1085 clk_sys.rate = clk_sys.parent->rate;
1086
1087 /* Compute the current ARM PLL and USB PLL frequencies */
1088 local_update_armpll_rate();
1089
1090 /* Compute HCLK and PCLK bus rates */
1091 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1092 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1093
1094 /*
1095 * Enable system clocks - this step is somewhat formal, as the
1096 * clocks are already running, but it does get the clock data
1097 * inline with the actual system state. Never disable these
1098 * clocks as they will only stop if the system is going to sleep.
1099 * In that case, the chip/system power management functions will
1100 * handle clock gating.
1101 */
1102 if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1103 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1104
1105 /*
1106 * Timers 0 and 1 were enabled and are being used by the high
1107 * resolution tick function prior to this driver being initialized.
1108 * Tag them now as used.
1109 */
1110 if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1111 printk(KERN_ERR "Error enabling timer tick clocks\n");
1112
1113 return 0;
1114 }
1115 core_initcall(clk_init);
1116
Linux kernel - Deliverables
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