arch/arm/mach-mmp/time.c

   1 /*
   2  * linux/arch/arm/mach-mmp/time.c
   3  *
   4  *   Support for clocksource and clockevents
   5  *
   6  * Copyright (C) 2008 Marvell International Ltd.
   7  * All rights reserved.
   8  *
   9  *   2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
  10  *   2008-10-08: Bin Yang <bin.yang@marvell.com>
  11  *
  12  * The timers module actually includes three timers, each timer with up to
  13  * three match comparators. Timer #0 is used here in free-running mode as
  14  * the clock source, and match comparator #1 used as clock event device.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/clockchips.h>
  25
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/sched_clock.h>
  32
  33 #include <mach/addr-map.h>
  34 #include <mach/regs-timers.h>
  35 #include <mach/regs-apbc.h>
  36 #include <mach/irqs.h>
  37 #include <mach/cputype.h>
  38 #include <asm/mach/time.h>
  39
  40 #include "clock.h"
  41
  42 #ifdef CONFIG_CPU_MMP2
  43 #define MMP_CLOCK_FREQ          6500000
  44 #else
  45 #define MMP_CLOCK_FREQ          3250000
  46 #endif
  47
  48 #define TIMERS_VIRT_BASE        TIMERS1_VIRT_BASE
  49
  50 #define MAX_DELTA               (0xfffffffe)
  51 #define MIN_DELTA               (16)
  52
  53 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
  54
  55 /*
  56  * FIXME: the timer needs some delay to stablize the counter capture
  57  */
  58 static inline uint32_t timer_read(void)
  59 {
  60         int delay = 100;
  61
  62         __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
  63
  64         while (delay--)
  65                 cpu_relax();
  66
  67         return __raw_readl(mmp_timer_base + TMR_CVWR(1));
  68 }
  69
  70 static u64 notrace mmp_read_sched_clock(void)
  71 {
  72         return timer_read();
  73 }
  74
  75 static irqreturn_t timer_interrupt(int irq, void *dev_id)
  76 {
  77         struct clock_event_device *c = dev_id;
  78
  79         /*
  80          * Clear pending interrupt status.
  81          */
  82         __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
  83
  84         /*
  85          * Disable timer 0.
  86          */
  87         __raw_writel(0x02, mmp_timer_base + TMR_CER);
  88
  89         c->event_handler(c);
  90
  91         return IRQ_HANDLED;
  92 }
  93
  94 static int timer_set_next_event(unsigned long delta,
  95                                 struct clock_event_device *dev)
  96 {
  97         unsigned long flags;
  98
  99         local_irq_save(flags);
 100
 101         /*
 102          * Disable timer 0.
 103          */
 104         __raw_writel(0x02, mmp_timer_base + TMR_CER);
 105
 106         /*
 107          * Clear and enable timer match 0 interrupt.
 108          */
 109         __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
 110         __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
 111
 112         /*
 113          * Setup new clockevent timer value.
 114          */
 115         __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
 116
 117         /*
 118          * Enable timer 0.
 119          */
 120         __raw_writel(0x03, mmp_timer_base + TMR_CER);
 121
 122         local_irq_restore(flags);
 123
 124         return 0;
 125 }
 126
 127 static int timer_set_shutdown(struct clock_event_device *evt)
 128 {
 129         unsigned long flags;
 130
 131         local_irq_save(flags);
 132         /* disable the matching interrupt */
 133         __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
 134         local_irq_restore(flags);
 135
 136         return 0;
 137 }
 138
 139 static struct clock_event_device ckevt = {
 140         .name                   = "clockevent",
 141         .features               = CLOCK_EVT_FEAT_ONESHOT,
 142         .rating                 = 200,
 143         .set_next_event         = timer_set_next_event,
 144         .set_state_shutdown     = timer_set_shutdown,
 145         .set_state_oneshot      = timer_set_shutdown,
 146 };
 147
 148 static cycle_t clksrc_read(struct clocksource *cs)
 149 {
 150         return timer_read();
 151 }
 152
 153 static struct clocksource cksrc = {
 154         .name           = "clocksource",
 155         .rating         = 200,
 156         .read           = clksrc_read,
 157         .mask           = CLOCKSOURCE_MASK(32),
 158         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 159 };
 160
 161 static void __init timer_config(void)
 162 {
 163         uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
 164
 165         __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
 166
 167         ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
 168                 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
 169         __raw_writel(ccr, mmp_timer_base + TMR_CCR);
 170
 171         /* set timer 0 to periodic mode, and timer 1 to free-running mode */
 172         __raw_writel(0x2, mmp_timer_base + TMR_CMR);
 173
 174         __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
 175         __raw_writel(0x7, mmp_timer_base + TMR_ICR(0));  /* clear status */
 176         __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
 177
 178         __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
 179         __raw_writel(0x7, mmp_timer_base + TMR_ICR(1));  /* clear status */
 180         __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
 181
 182         /* enable timer 1 counter */
 183         __raw_writel(0x2, mmp_timer_base + TMR_CER);
 184 }
 185
 186 static struct irqaction timer_irq = {
 187         .name           = "timer",
 188         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 189         .handler        = timer_interrupt,
 190         .dev_id         = &ckevt,
 191 };
 192
 193 void __init timer_init(int irq)
 194 {
 195         timer_config();
 196
 197         sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
 198
 199         ckevt.cpumask = cpumask_of(0);
 200
 201         setup_irq(irq, &timer_irq);
 202
 203         clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
 204         clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
 205                                         MIN_DELTA, MAX_DELTA);
 206 }
 207
 208 #ifdef CONFIG_OF
 209 static const struct of_device_id mmp_timer_dt_ids[] = {
 210         { .compatible = "mrvl,mmp-timer", },
 211         {}
 212 };
 213
 214 void __init mmp_dt_init_timer(void)
 215 {
 216         struct device_node *np;
 217         int irq, ret;
 218
 219         np = of_find_matching_node(NULL, mmp_timer_dt_ids);
 220         if (!np) {
 221                 ret = -ENODEV;
 222                 goto out;
 223         }
 224
 225         irq = irq_of_parse_and_map(np, 0);
 226         if (!irq) {
 227                 ret = -EINVAL;
 228                 goto out;
 229         }
 230         mmp_timer_base = of_iomap(np, 0);
 231         if (!mmp_timer_base) {
 232                 ret = -ENOMEM;
 233                 goto out;
 234         }
 235         timer_init(irq);
 236         return;
 237 out:
 238         pr_err("Failed to get timer from device tree with error:%d\n", ret);
 239 }
 240 #endif