arch/arm/mach-msm/smd_private.h

   1 /* arch/arm/mach-msm/smd_private.h
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2007 QUALCOMM Incorporated
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16 #ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
  17 #define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
  18
  19 struct smem_heap_info
  20 {
  21         unsigned initialized;
  22         unsigned free_offset;
  23         unsigned heap_remaining;
  24         unsigned reserved;
  25 };
  26
  27 struct smem_heap_entry
  28 {
  29         unsigned allocated;
  30         unsigned offset;
  31         unsigned size;
  32         unsigned reserved;
  33 };
  34
  35 struct smem_proc_comm
  36 {
  37         unsigned command;
  38         unsigned status;
  39         unsigned data1;
  40         unsigned data2;
  41 };
  42
  43 #define PC_APPS  0
  44 #define PC_MODEM 1
  45
  46 #define VERSION_SMD       0
  47 #define VERSION_QDSP6     4
  48 #define VERSION_APPS_SBL  6
  49 #define VERSION_MODEM_SBL 7
  50 #define VERSION_APPS      8
  51 #define VERSION_MODEM     9
  52
  53 struct smem_shared
  54 {
  55         struct smem_proc_comm proc_comm[4];
  56         unsigned version[32];
  57         struct smem_heap_info heap_info;
  58         struct smem_heap_entry heap_toc[512];
  59 };
  60
  61 #define SMSM_V1_SIZE            (sizeof(unsigned) * 8)
  62 #define SMSM_V2_SIZE            (sizeof(unsigned) * 4)
  63
  64 struct smsm_interrupt_info
  65 {
  66         uint32_t aArm_en_mask;
  67         uint32_t aArm_interrupts_pending;
  68         uint32_t aArm_wakeup_reason;
  69 };
  70
  71 #define SZ_DIAG_ERR_MSG 0xC8
  72 #define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
  73 #define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
  74 #define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
  75 #define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
  76
  77 #define SMSM_INIT               0x00000001
  78 #define SMSM_SMDINIT            0x00000008
  79 #define SMSM_RPCINIT            0x00000020
  80 #define SMSM_RESET              0x00000040
  81 #define SMSM_RSA                0x00000080
  82 #define SMSM_RUN                0x00000100
  83 #define SMSM_PWRC               0x00000200
  84 #define SMSM_TIMEWAIT           0x00000400
  85 #define SMSM_TIMEINIT           0x00000800
  86 #define SMSM_PWRC_EARLY_EXIT    0x00001000
  87 #define SMSM_WFPI               0x00002000
  88 #define SMSM_SLEEP              0x00004000
  89 #define SMSM_SLEEPEXIT          0x00008000
  90 #define SMSM_APPS_REBOOT        0x00020000
  91 #define SMSM_SYSTEM_POWER_DOWN  0x00040000
  92 #define SMSM_SYSTEM_REBOOT      0x00080000
  93 #define SMSM_SYSTEM_DOWNLOAD    0x00100000
  94 #define SMSM_PWRC_SUSPEND       0x00200000
  95 #define SMSM_APPS_SHUTDOWN      0x00400000
  96 #define SMSM_SMD_LOOPBACK       0x00800000
  97 #define SMSM_RUN_QUIET          0x01000000
  98 #define SMSM_MODEM_WAIT         0x02000000
  99 #define SMSM_MODEM_BREAK        0x04000000
 100 #define SMSM_MODEM_CONTINUE     0x08000000
 101 #define SMSM_UNKNOWN            0x80000000
 102
 103 #define SMSM_WKUP_REASON_RPC    0x00000001
 104 #define SMSM_WKUP_REASON_INT    0x00000002
 105 #define SMSM_WKUP_REASON_GPIO   0x00000004
 106 #define SMSM_WKUP_REASON_TIMER  0x00000008
 107 #define SMSM_WKUP_REASON_ALARM  0x00000010
 108 #define SMSM_WKUP_REASON_RESET  0x00000020
 109
 110 #ifndef CONFIG_ARCH_MSM_SCORPION
 111 enum smsm_state_item {
 112         SMSM_STATE_APPS = 1,
 113         SMSM_STATE_MODEM = 3,
 114         SMSM_STATE_COUNT,
 115 };
 116 #else
 117 enum smsm_state_item {
 118         SMSM_STATE_APPS,
 119         SMSM_STATE_MODEM,
 120         SMSM_STATE_HEXAGON,
 121         SMSM_STATE_APPS_DEM,
 122         SMSM_STATE_MODEM_DEM,
 123         SMSM_STATE_QDSP6_DEM,
 124         SMSM_STATE_POWER_MASTER_DEM,
 125         SMSM_STATE_TIME_MASTER_DEM,
 126         SMSM_STATE_COUNT,
 127 };
 128 #endif
 129
 130 void *smem_alloc(unsigned id, unsigned size);
 131 int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
 132 uint32_t smsm_get_state(enum smsm_state_item item);
 133 int smsm_set_sleep_duration(uint32_t delay);
 134 int smsm_set_interrupt_info(struct smsm_interrupt_info *info);
 135 void smsm_print_sleep_info(void);
 136
 137 #define SMEM_NUM_SMD_CHANNELS        64
 138
 139 typedef enum
 140 {
 141         /* fixed items */
 142         SMEM_PROC_COMM = 0,
 143         SMEM_HEAP_INFO,
 144         SMEM_ALLOCATION_TABLE,
 145         SMEM_VERSION_INFO,
 146         SMEM_HW_RESET_DETECT,
 147         SMEM_AARM_WARM_BOOT,
 148         SMEM_DIAG_ERR_MESSAGE,
 149         SMEM_SPINLOCK_ARRAY,
 150         SMEM_MEMORY_BARRIER_LOCATION,
 151
 152         /* dynamic items */
 153         SMEM_AARM_PARTITION_TABLE,
 154         SMEM_AARM_BAD_BLOCK_TABLE,
 155         SMEM_RESERVE_BAD_BLOCKS,
 156         SMEM_WM_UUID,
 157         SMEM_CHANNEL_ALLOC_TBL,
 158         SMEM_SMD_BASE_ID,
 159         SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
 160         SMEM_SMEM_LOG_EVENTS,
 161         SMEM_SMEM_STATIC_LOG_IDX,
 162         SMEM_SMEM_STATIC_LOG_EVENTS,
 163         SMEM_SMEM_SLOW_CLOCK_SYNC,
 164         SMEM_SMEM_SLOW_CLOCK_VALUE,
 165         SMEM_BIO_LED_BUF,
 166         SMEM_SMSM_SHARED_STATE,
 167         SMEM_SMSM_INT_INFO,
 168         SMEM_SMSM_SLEEP_DELAY,
 169         SMEM_SMSM_LIMIT_SLEEP,
 170         SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
 171         SMEM_KEYPAD_KEYS_PRESSED,
 172         SMEM_KEYPAD_STATE_UPDATED,
 173         SMEM_KEYPAD_STATE_IDX,
 174         SMEM_GPIO_INT,
 175         SMEM_MDDI_LCD_IDX,
 176         SMEM_MDDI_HOST_DRIVER_STATE,
 177         SMEM_MDDI_LCD_DISP_STATE,
 178         SMEM_LCD_CUR_PANEL,
 179         SMEM_MARM_BOOT_SEGMENT_INFO,
 180         SMEM_AARM_BOOT_SEGMENT_INFO,
 181         SMEM_SLEEP_STATIC,
 182         SMEM_SCORPION_FREQUENCY,
 183         SMEM_SMD_PROFILES,
 184         SMEM_TSSC_BUSY,
 185         SMEM_HS_SUSPEND_FILTER_INFO,
 186         SMEM_BATT_INFO,
 187         SMEM_APPS_BOOT_MODE,
 188         SMEM_VERSION_FIRST,
 189         SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
 190         SMEM_OSS_RRCASN1_BUF1,
 191         SMEM_OSS_RRCASN1_BUF2,
 192         SMEM_ID_VENDOR0,
 193         SMEM_ID_VENDOR1,
 194         SMEM_ID_VENDOR2,
 195         SMEM_HW_SW_BUILD_ID,
 196         SMEM_SMD_BLOCK_PORT_BASE_ID,
 197         SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
 198         SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
 199         SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
 200         SMEM_SCLK_CONVERSION,
 201         SMEM_SMD_SMSM_INTR_MUX,
 202         SMEM_SMSM_CPU_INTR_MASK,
 203         SMEM_APPS_DEM_SLAVE_DATA,
 204         SMEM_QDSP6_DEM_SLAVE_DATA,
 205         SMEM_CLKREGIM_BSP,
 206         SMEM_CLKREGIM_SOURCES,
 207         SMEM_SMD_FIFO_BASE_ID,
 208         SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
 209         SMEM_POWER_ON_STATUS_INFO,
 210         SMEM_DAL_AREA,
 211         SMEM_SMEM_LOG_POWER_IDX,
 212         SMEM_SMEM_LOG_POWER_WRAP,
 213         SMEM_SMEM_LOG_POWER_EVENTS,
 214         SMEM_ERR_CRASH_LOG,
 215         SMEM_ERR_F3_TRACE_LOG,
 216         SMEM_NUM_ITEMS,
 217 } smem_mem_type;
 218
 219 #endif