arch/arm/mach-msm/timer.c

   1 /*
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clocksource.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <asm/mach/time.h>
  28 #include <asm/hardware/gic.h>
  29 #include <asm/localtimer.h>
  30 #include <asm/sched_clock.h>
  31
  32 #include "common.h"
  33
  34 #define TIMER_MATCH_VAL         0x0000
  35 #define TIMER_COUNT_VAL         0x0004
  36 #define TIMER_ENABLE            0x0008
  37 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
  38 #define TIMER_ENABLE_EN                 BIT(0)
  39 #define TIMER_CLEAR             0x000C
  40 #define DGT_CLK_CTL             0x0030
  41 #define DGT_CLK_CTL_DIV_4       0x3
  42
  43 #define GPT_HZ 32768
  44
  45 #define MSM_DGT_SHIFT 5
  46
  47 static void __iomem *event_base;
  48
  49 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  50 {
  51         struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
  52         /* Stop the timer tick */
  53         if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  54                 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  55                 ctrl &= ~TIMER_ENABLE_EN;
  56                 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  57         }
  58         evt->event_handler(evt);
  59         return IRQ_HANDLED;
  60 }
  61
  62 static int msm_timer_set_next_event(unsigned long cycles,
  63                                     struct clock_event_device *evt)
  64 {
  65         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  66
  67         writel_relaxed(0, event_base + TIMER_CLEAR);
  68         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
  69         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
  70         return 0;
  71 }
  72
  73 static void msm_timer_set_mode(enum clock_event_mode mode,
  74                               struct clock_event_device *evt)
  75 {
  76         u32 ctrl;
  77
  78         ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  79         ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
  80
  81         switch (mode) {
  82         case CLOCK_EVT_MODE_RESUME:
  83         case CLOCK_EVT_MODE_PERIODIC:
  84                 break;
  85         case CLOCK_EVT_MODE_ONESHOT:
  86                 /* Timer is enabled in set_next_event */
  87                 break;
  88         case CLOCK_EVT_MODE_UNUSED:
  89         case CLOCK_EVT_MODE_SHUTDOWN:
  90                 break;
  91         }
  92         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  93 }
  94
  95 static struct clock_event_device msm_clockevent = {
  96         .name           = "gp_timer",
  97         .features       = CLOCK_EVT_FEAT_ONESHOT,
  98         .rating         = 200,
  99         .set_next_event = msm_timer_set_next_event,
 100         .set_mode       = msm_timer_set_mode,
 101 };
 102
 103 static union {
 104         struct clock_event_device *evt;
 105         struct clock_event_device __percpu **percpu_evt;
 106 } msm_evt;
 107
 108 static void __iomem *source_base;
 109
 110 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
 111 {
 112         return readl_relaxed(source_base + TIMER_COUNT_VAL);
 113 }
 114
 115 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
 116 {
 117         /*
 118          * Shift timer count down by a constant due to unreliable lower bits
 119          * on some targets.
 120          */
 121         return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
 122 }
 123
 124 static struct clocksource msm_clocksource = {
 125         .name   = "dg_timer",
 126         .rating = 300,
 127         .read   = msm_read_timer_count,
 128         .mask   = CLOCKSOURCE_MASK(32),
 129         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 130 };
 131
 132 #ifdef CONFIG_LOCAL_TIMERS
 133 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 134 {
 135         /* Use existing clock_event for cpu 0 */
 136         if (!smp_processor_id())
 137                 return 0;
 138
 139         writel_relaxed(0, event_base + TIMER_ENABLE);
 140         writel_relaxed(0, event_base + TIMER_CLEAR);
 141         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
 142         evt->irq = msm_clockevent.irq;
 143         evt->name = "local_timer";
 144         evt->features = msm_clockevent.features;
 145         evt->rating = msm_clockevent.rating;
 146         evt->set_mode = msm_timer_set_mode;
 147         evt->set_next_event = msm_timer_set_next_event;
 148         evt->shift = msm_clockevent.shift;
 149         evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
 150         evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
 151         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 152
 153         *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
 154         clockevents_register_device(evt);
 155         enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
 156         return 0;
 157 }
 158
 159 static void msm_local_timer_stop(struct clock_event_device *evt)
 160 {
 161         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 162         disable_percpu_irq(evt->irq);
 163 }
 164
 165 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
 166         .setup  = msm_local_timer_setup,
 167         .stop   = msm_local_timer_stop,
 168 };
 169 #endif /* CONFIG_LOCAL_TIMERS */
 170
 171 static notrace u32 msm_sched_clock_read(void)
 172 {
 173         return msm_clocksource.read(&msm_clocksource);
 174 }
 175
 176 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
 177                                   bool percpu)
 178 {
 179         struct clock_event_device *ce = &msm_clockevent;
 180         struct clocksource *cs = &msm_clocksource;
 181         int res;
 182
 183         writel_relaxed(0, event_base + TIMER_ENABLE);
 184         writel_relaxed(0, event_base + TIMER_CLEAR);
 185         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
 186         ce->cpumask = cpumask_of(0);
 187         ce->irq = irq;
 188
 189         clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
 190         if (percpu) {
 191                 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
 192                 if (!msm_evt.percpu_evt) {
 193                         pr_err("memory allocation failed for %s\n", ce->name);
 194                         goto err;
 195                 }
 196                 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
 197                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
 198                                          ce->name, msm_evt.percpu_evt);
 199                 if (!res) {
 200                         enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
 201 #ifdef CONFIG_LOCAL_TIMERS
 202                         local_timer_register(&msm_local_timer_ops);
 203 #endif
 204                 }
 205         } else {
 206                 msm_evt.evt = ce;
 207                 res = request_irq(ce->irq, msm_timer_interrupt,
 208                                   IRQF_TIMER | IRQF_NOBALANCING |
 209                                   IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
 210         }
 211
 212         if (res)
 213                 pr_err("request_irq failed for %s\n", ce->name);
 214 err:
 215         writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
 216         res = clocksource_register_hz(cs, dgt_hz);
 217         if (res)
 218                 pr_err("clocksource_register failed\n");
 219         setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
 220 }
 221
 222 #ifdef CONFIG_OF
 223 static const struct of_device_id msm_dgt_match[] __initconst = {
 224         { .compatible = "qcom,msm-dgt" },
 225         { },
 226 };
 227
 228 static const struct of_device_id msm_gpt_match[] __initconst = {
 229         { .compatible = "qcom,msm-gpt" },
 230         { },
 231 };
 232
 233 static void __init msm_dt_timer_init(void)
 234 {
 235         struct device_node *np;
 236         u32 freq;
 237         int irq;
 238         struct resource res;
 239         u32 percpu_offset;
 240         void __iomem *dgt_clk_ctl;
 241
 242         np = of_find_matching_node(NULL, msm_gpt_match);
 243         if (!np) {
 244                 pr_err("Can't find GPT DT node\n");
 245                 return;
 246         }
 247
 248         event_base = of_iomap(np, 0);
 249         if (!event_base) {
 250                 pr_err("Failed to map event base\n");
 251                 return;
 252         }
 253
 254         irq = irq_of_parse_and_map(np, 0);
 255         if (irq <= 0) {
 256                 pr_err("Can't get irq\n");
 257                 return;
 258         }
 259         of_node_put(np);
 260
 261         np = of_find_matching_node(NULL, msm_dgt_match);
 262         if (!np) {
 263                 pr_err("Can't find DGT DT node\n");
 264                 return;
 265         }
 266
 267         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
 268                 percpu_offset = 0;
 269
 270         if (of_address_to_resource(np, 0, &res)) {
 271                 pr_err("Failed to parse DGT resource\n");
 272                 return;
 273         }
 274
 275         source_base = ioremap(res.start + percpu_offset, resource_size(&res));
 276         if (!source_base) {
 277                 pr_err("Failed to map source base\n");
 278                 return;
 279         }
 280
 281         if (!of_address_to_resource(np, 1, &res)) {
 282                 dgt_clk_ctl = ioremap(res.start + percpu_offset,
 283                                       resource_size(&res));
 284                 if (!dgt_clk_ctl) {
 285                         pr_err("Failed to map DGT control base\n");
 286                         return;
 287                 }
 288                 writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
 289                 iounmap(dgt_clk_ctl);
 290         }
 291
 292         if (of_property_read_u32(np, "clock-frequency", &freq)) {
 293                 pr_err("Unknown frequency\n");
 294                 return;
 295         }
 296         of_node_put(np);
 297
 298         msm_timer_init(freq, 32, irq, !!percpu_offset);
 299 }
 300
 301 struct sys_timer msm_dt_timer = {
 302         .init = msm_dt_timer_init
 303 };
 304 #endif
 305
 306 static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
 307 {
 308         event_base = ioremap(event, SZ_64);
 309         if (!event_base) {
 310                 pr_err("Failed to map event base\n");
 311                 return 1;
 312         }
 313         source_base = ioremap(source, SZ_64);
 314         if (!source_base) {
 315                 pr_err("Failed to map source base\n");
 316                 return 1;
 317         }
 318         return 0;
 319 }
 320
 321 static void __init msm7x01_timer_init(void)
 322 {
 323         struct clocksource *cs = &msm_clocksource;
 324
 325         if (msm_timer_map(0xc0100000, 0xc0100010))
 326                 return;
 327         cs->read = msm_read_timer_count_shift;
 328         cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
 329         /* 600 KHz */
 330         msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
 331                         false);
 332 }
 333
 334 struct sys_timer msm7x01_timer = {
 335         .init = msm7x01_timer_init
 336 };
 337
 338 static void __init msm7x30_timer_init(void)
 339 {
 340         if (msm_timer_map(0xc0100004, 0xc0100024))
 341                 return;
 342         msm_timer_init(24576000 / 4, 32, 1, false);
 343 }
 344
 345 struct sys_timer msm7x30_timer = {
 346         .init = msm7x30_timer_init
 347 };
 348
 349 static void __init msm8x60_timer_init(void)
 350 {
 351         if (msm_timer_map(0x02000004, 0x02040024))
 352                 return;
 353         writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
 354         msm_timer_init(27000000 / 4, 32, 17, true);
 355 }
 356
 357 struct sys_timer msm8x60_timer = {
 358         .init = msm8x60_timer_init
 359 };
 360
 361 static void __init msm8960_timer_init(void)
 362 {
 363         if (msm_timer_map(0x0200A004, 0x0208A024))
 364                 return;
 365         writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
 366         msm_timer_init(27000000 / 4, 32, 17, true);
 367 }
 368
 369 struct sys_timer msm8960_timer = {
 370         .init = msm8960_timer_init
 371 };
 372
 373 static void __init qsd8x50_timer_init(void)
 374 {
 375         if (msm_timer_map(0xAC100000, 0xAC100010))
 376                 return;
 377         msm_timer_init(19200000 / 4, 32, 7, false);
 378 }
 379
 380 struct sys_timer qsd8x50_timer = {
 381         .init = qsd8x50_timer_init
 382 };