arch/arm/mach-msm/timer.c

   1 /*
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clocksource.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/mach/time.h>
  25 #include <asm/hardware/gic.h>
  26 #include <asm/localtimer.h>
  27
  28 #include <mach/msm_iomap.h>
  29 #include <mach/cpu.h>
  30 #include <mach/board.h>
  31
  32 #define TIMER_MATCH_VAL         0x0000
  33 #define TIMER_COUNT_VAL         0x0004
  34 #define TIMER_ENABLE            0x0008
  35 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
  36 #define TIMER_ENABLE_EN                 BIT(0)
  37 #define TIMER_CLEAR             0x000C
  38 #define DGT_CLK_CTL             0x0034
  39 #define DGT_CLK_CTL_DIV_4       0x3
  40
  41 #define GPT_HZ 32768
  42
  43 #define MSM_DGT_SHIFT 5
  44
  45 static void __iomem *event_base;
  46
  47 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  48 {
  49         struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
  50         /* Stop the timer tick */
  51         if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  52                 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  53                 ctrl &= ~TIMER_ENABLE_EN;
  54                 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  55         }
  56         evt->event_handler(evt);
  57         return IRQ_HANDLED;
  58 }
  59
  60 static int msm_timer_set_next_event(unsigned long cycles,
  61                                     struct clock_event_device *evt)
  62 {
  63         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  64
  65         writel_relaxed(0, event_base + TIMER_CLEAR);
  66         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
  67         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
  68         return 0;
  69 }
  70
  71 static void msm_timer_set_mode(enum clock_event_mode mode,
  72                               struct clock_event_device *evt)
  73 {
  74         u32 ctrl;
  75
  76         ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  77         ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
  78
  79         switch (mode) {
  80         case CLOCK_EVT_MODE_RESUME:
  81         case CLOCK_EVT_MODE_PERIODIC:
  82                 break;
  83         case CLOCK_EVT_MODE_ONESHOT:
  84                 /* Timer is enabled in set_next_event */
  85                 break;
  86         case CLOCK_EVT_MODE_UNUSED:
  87         case CLOCK_EVT_MODE_SHUTDOWN:
  88                 break;
  89         }
  90         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  91 }
  92
  93 static struct clock_event_device msm_clockevent = {
  94         .name           = "gp_timer",
  95         .features       = CLOCK_EVT_FEAT_ONESHOT,
  96         .rating         = 200,
  97         .set_next_event = msm_timer_set_next_event,
  98         .set_mode       = msm_timer_set_mode,
  99 };
 100
 101 static union {
 102         struct clock_event_device *evt;
 103         struct clock_event_device __percpu **percpu_evt;
 104 } msm_evt;
 105
 106 static void __iomem *source_base;
 107
 108 static cycle_t msm_read_timer_count(struct clocksource *cs)
 109 {
 110         return readl_relaxed(source_base + TIMER_COUNT_VAL);
 111 }
 112
 113 static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
 114 {
 115         /*
 116          * Shift timer count down by a constant due to unreliable lower bits
 117          * on some targets.
 118          */
 119         return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
 120 }
 121
 122 static struct clocksource msm_clocksource = {
 123         .name   = "dg_timer",
 124         .rating = 300,
 125         .read   = msm_read_timer_count,
 126         .mask   = CLOCKSOURCE_MASK(32),
 127         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 128 };
 129
 130 #ifdef CONFIG_LOCAL_TIMERS
 131 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 132 {
 133         /* Use existing clock_event for cpu 0 */
 134         if (!smp_processor_id())
 135                 return 0;
 136
 137         writel_relaxed(0, event_base + TIMER_ENABLE);
 138         writel_relaxed(0, event_base + TIMER_CLEAR);
 139         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
 140         evt->irq = msm_clockevent.irq;
 141         evt->name = "local_timer";
 142         evt->features = msm_clockevent.features;
 143         evt->rating = msm_clockevent.rating;
 144         evt->set_mode = msm_timer_set_mode;
 145         evt->set_next_event = msm_timer_set_next_event;
 146         evt->shift = msm_clockevent.shift;
 147         evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
 148         evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
 149         evt->min_delta_ns = clockevent_delta2ns(4, evt);
 150
 151         *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
 152         clockevents_register_device(evt);
 153         enable_percpu_irq(evt->irq, 0);
 154         return 0;
 155 }
 156
 157 static void msm_local_timer_stop(struct clock_event_device *evt)
 158 {
 159         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 160         disable_percpu_irq(evt->irq);
 161 }
 162
 163 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
 164         .setup  = msm_local_timer_setup,
 165         .stop   = msm_local_timer_stop,
 166 };
 167 #endif /* CONFIG_LOCAL_TIMERS */
 168
 169 static void __init msm_timer_init(void)
 170 {
 171         struct clock_event_device *ce = &msm_clockevent;
 172         struct clocksource *cs = &msm_clocksource;
 173         int res;
 174         u32 dgt_hz;
 175
 176         if (cpu_is_msm7x01()) {
 177                 event_base = MSM_CSR_BASE;
 178                 source_base = MSM_CSR_BASE + 0x10;
 179                 dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
 180                 cs->read = msm_read_timer_count_shift;
 181                 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
 182         } else if (cpu_is_msm7x30()) {
 183                 event_base = MSM_CSR_BASE + 0x04;
 184                 source_base = MSM_CSR_BASE + 0x24;
 185                 dgt_hz = 24576000 / 4;
 186         } else if (cpu_is_qsd8x50()) {
 187                 event_base = MSM_CSR_BASE;
 188                 source_base = MSM_CSR_BASE + 0x10;
 189                 dgt_hz = 19200000 / 4;
 190         } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
 191                 event_base = MSM_TMR_BASE + 0x04;
 192                 /* Use CPU0's timer as the global clock source. */
 193                 source_base = MSM_TMR0_BASE + 0x24;
 194                 dgt_hz = 27000000 / 4;
 195                 writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 196         } else
 197                 BUG();
 198
 199         writel_relaxed(0, event_base + TIMER_ENABLE);
 200         writel_relaxed(0, event_base + TIMER_CLEAR);
 201         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
 202         ce->cpumask = cpumask_of(0);
 203
 204         ce->irq = INT_GP_TIMER_EXP;
 205         clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
 206         if (cpu_is_msm8x60() || cpu_is_msm8960()) {
 207                 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
 208                 if (!msm_evt.percpu_evt) {
 209                         pr_err("memory allocation failed for %s\n", ce->name);
 210                         goto err;
 211                 }
 212                 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
 213                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
 214                                          ce->name, msm_evt.percpu_evt);
 215                 if (!res) {
 216                         enable_percpu_irq(ce->irq, 0);
 217 #ifdef CONFIG_LOCAL_TIMERS
 218                         local_timer_register(&msm_local_timer_ops);
 219 #endif
 220                 }
 221         } else {
 222                 msm_evt.evt = ce;
 223                 res = request_irq(ce->irq, msm_timer_interrupt,
 224                                   IRQF_TIMER | IRQF_NOBALANCING |
 225                                   IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
 226         }
 227
 228         if (res)
 229                 pr_err("request_irq failed for %s\n", ce->name);
 230 err:
 231         writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
 232         res = clocksource_register_hz(cs, dgt_hz);
 233         if (res)
 234                 pr_err("clocksource_register failed\n");
 235 }
 236
 237 struct sys_timer msm_timer = {
 238         .init = msm_timer_init
 239 };