arch/arm/mach-mv78xx0/addr-map.c

   1 /*
   2  * arch/arm/mach-mv78xx0/addr-map.c
   3  *
   4  * Address map functions for Marvell MV78xx0 SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/mbus.h>
  14 #include <linux/io.h>
  15 #include <plat/addr-map.h>
  16 #include <mach/mv78xx0.h>
  17 #include "common.h"
  18
  19 /*
  20  * Generic Address Decode Windows bit settings
  21  */
  22 #define TARGET_DEV_BUS          1
  23 #define TARGET_PCIE0            4
  24 #define TARGET_PCIE1            8
  25 #define TARGET_PCIE(i)          ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
  26 #define ATTR_DEV_SPI_ROM        0x1f
  27 #define ATTR_DEV_BOOT           0x2f
  28 #define ATTR_DEV_CS3            0x37
  29 #define ATTR_DEV_CS2            0x3b
  30 #define ATTR_DEV_CS1            0x3d
  31 #define ATTR_DEV_CS0            0x3e
  32 #define ATTR_PCIE_IO(l)         (0xf0 & ~(0x10 << (l)))
  33 #define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
  34
  35 /*
  36  * CPU Address Decode Windows registers
  37  */
  38 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
  39 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
  40
  41 static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
  42 {
  43         /*
  44          * Find the control register base address for this window.
  45          *
  46          * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
  47          * MBUS bridge depending on which CPU core we're running on,
  48          * so we don't need to take that into account here.
  49          */
  50
  51         return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
  52 }
  53
  54 /*
  55  * Description of the windows needed by the platform code
  56  */
  57 static struct orion_addr_map_cfg addr_map_cfg __initdata = {
  58         .num_wins = 14,
  59         .remappable_wins = 8,
  60         .win_cfg_base = win_cfg_base,
  61 };
  62
  63 void __init mv78xx0_setup_cpu_mbus(void)
  64 {
  65         /*
  66          * Disable, clear and configure windows.
  67          */
  68         orion_config_wins(&addr_map_cfg, NULL);
  69
  70         /*
  71          * Setup MBUS dram target info.
  72          */
  73         if (mv78xx0_core_index() == 0)
  74                 orion_setup_cpu_mbus_target(&addr_map_cfg,
  75                                             (void __iomem *) DDR_WINDOW_CPU0_BASE);
  76         else
  77                 orion_setup_cpu_mbus_target(&addr_map_cfg,
  78                                             (void __iomem *) DDR_WINDOW_CPU1_BASE);
  79 }
  80
  81 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
  82                                       int maj, int min)
  83 {
  84         orion_setup_cpu_win(&addr_map_cfg, window, base, size,
  85                             TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
  86 }
  87
  88 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
  89                                        int maj, int min)
  90 {
  91         orion_setup_cpu_win(&addr_map_cfg, window, base, size,
  92                             TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
  93 }