2 * arch/arm/mach-mv78xx0/common.c
4 * Core functions for Marvell MV78xx0 SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/mbus.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/ata_platform.h>
18 #include <asm/mach/map.h>
19 #include <asm/mach/time.h>
20 #include <mach/mv78xx0.h>
21 #include <plat/cache-feroceon-l2.h>
22 #include <plat/ehci-orion.h>
23 #include <plat/orion_nand.h>
24 #include <plat/time.h>
28 /*****************************************************************************
30 ****************************************************************************/
31 int mv78xx0_core_index(void)
36 * Read Extra Features register.
38 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra
));
40 return !!(extra
& 0x00004000);
43 static int get_hclk(void)
48 * HCLK tick rate is configured by DEV_D[7:5] pins.
50 switch ((readl(SAMPLE_AT_RESET_LOW
) >> 5) & 7) {
67 panic("unknown HCLK PLL setting: %.8x\n",
68 readl(SAMPLE_AT_RESET_LOW
));
74 static void get_pclk_l2clk(int hclk
, int core_index
, int *pclk
, int *l2clk
)
79 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
80 * PCLK/L2CLK by bits [19:14].
82 if (core_index
== 0) {
83 cfg
= (readl(SAMPLE_AT_RESET_LOW
) >> 8) & 0x3f;
85 cfg
= (readl(SAMPLE_AT_RESET_LOW
) >> 14) & 0x3f;
89 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
90 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
92 *pclk
= ((u64
)hclk
* (2 + (cfg
& 0xf))) >> 1;
95 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
98 *l2clk
= *pclk
/ (((cfg
>> 4) & 3) + 1);
101 static int get_tclk(void)
106 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
108 switch ((readl(SAMPLE_AT_RESET_HIGH
) >> 6) & 7) {
116 panic("unknown TCLK PLL setting: %.8x\n",
117 readl(SAMPLE_AT_RESET_HIGH
));
124 /*****************************************************************************
125 * I/O Address Mapping
126 ****************************************************************************/
127 static struct map_desc mv78xx0_io_desc
[] __initdata
= {
129 .virtual = MV78XX0_CORE_REGS_VIRT_BASE
,
131 .length
= MV78XX0_CORE_REGS_SIZE
,
134 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
135 .pfn
= __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
136 .length
= MV78XX0_PCIE_IO_SIZE
* 8,
139 .virtual = MV78XX0_REGS_VIRT_BASE
,
140 .pfn
= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE
),
141 .length
= MV78XX0_REGS_SIZE
,
146 void __init
mv78xx0_map_io(void)
151 * Map the right set of per-core registers depending on
152 * which core we are running on.
154 if (mv78xx0_core_index() == 0) {
155 phys
= MV78XX0_CORE0_REGS_PHYS_BASE
;
157 phys
= MV78XX0_CORE1_REGS_PHYS_BASE
;
159 mv78xx0_io_desc
[0].pfn
= __phys_to_pfn(phys
);
161 iotable_init(mv78xx0_io_desc
, ARRAY_SIZE(mv78xx0_io_desc
));
165 /*****************************************************************************
167 ****************************************************************************/
168 static struct orion_ehci_data mv78xx0_ehci_data
= {
169 .dram
= &mv78xx0_mbus_dram_info
,
170 .phy_version
= EHCI_PHY_NA
,
173 static u64 ehci_dmamask
= 0xffffffffUL
;
176 /*****************************************************************************
178 ****************************************************************************/
179 static struct resource mv78xx0_ehci0_resources
[] = {
181 .start
= USB0_PHYS_BASE
,
182 .end
= USB0_PHYS_BASE
+ 0x0fff,
183 .flags
= IORESOURCE_MEM
,
185 .start
= IRQ_MV78XX0_USB_0
,
186 .end
= IRQ_MV78XX0_USB_0
,
187 .flags
= IORESOURCE_IRQ
,
191 static struct platform_device mv78xx0_ehci0
= {
192 .name
= "orion-ehci",
195 .dma_mask
= &ehci_dmamask
,
196 .coherent_dma_mask
= 0xffffffff,
197 .platform_data
= &mv78xx0_ehci_data
,
199 .resource
= mv78xx0_ehci0_resources
,
200 .num_resources
= ARRAY_SIZE(mv78xx0_ehci0_resources
),
203 void __init
mv78xx0_ehci0_init(void)
205 platform_device_register(&mv78xx0_ehci0
);
209 /*****************************************************************************
211 ****************************************************************************/
212 static struct resource mv78xx0_ehci1_resources
[] = {
214 .start
= USB1_PHYS_BASE
,
215 .end
= USB1_PHYS_BASE
+ 0x0fff,
216 .flags
= IORESOURCE_MEM
,
218 .start
= IRQ_MV78XX0_USB_1
,
219 .end
= IRQ_MV78XX0_USB_1
,
220 .flags
= IORESOURCE_IRQ
,
224 static struct platform_device mv78xx0_ehci1
= {
225 .name
= "orion-ehci",
228 .dma_mask
= &ehci_dmamask
,
229 .coherent_dma_mask
= 0xffffffff,
230 .platform_data
= &mv78xx0_ehci_data
,
232 .resource
= mv78xx0_ehci1_resources
,
233 .num_resources
= ARRAY_SIZE(mv78xx0_ehci1_resources
),
236 void __init
mv78xx0_ehci1_init(void)
238 platform_device_register(&mv78xx0_ehci1
);
242 /*****************************************************************************
244 ****************************************************************************/
245 static struct resource mv78xx0_ehci2_resources
[] = {
247 .start
= USB2_PHYS_BASE
,
248 .end
= USB2_PHYS_BASE
+ 0x0fff,
249 .flags
= IORESOURCE_MEM
,
251 .start
= IRQ_MV78XX0_USB_2
,
252 .end
= IRQ_MV78XX0_USB_2
,
253 .flags
= IORESOURCE_IRQ
,
257 static struct platform_device mv78xx0_ehci2
= {
258 .name
= "orion-ehci",
261 .dma_mask
= &ehci_dmamask
,
262 .coherent_dma_mask
= 0xffffffff,
263 .platform_data
= &mv78xx0_ehci_data
,
265 .resource
= mv78xx0_ehci2_resources
,
266 .num_resources
= ARRAY_SIZE(mv78xx0_ehci2_resources
),
269 void __init
mv78xx0_ehci2_init(void)
271 platform_device_register(&mv78xx0_ehci2
);
275 /*****************************************************************************
277 ****************************************************************************/
278 struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data
= {
280 .dram
= &mv78xx0_mbus_dram_info
,
283 static struct resource mv78xx0_ge00_shared_resources
[] = {
286 .start
= GE00_PHYS_BASE
+ 0x2000,
287 .end
= GE00_PHYS_BASE
+ 0x3fff,
288 .flags
= IORESOURCE_MEM
,
290 .name
= "ge err irq",
291 .start
= IRQ_MV78XX0_GE_ERR
,
292 .end
= IRQ_MV78XX0_GE_ERR
,
293 .flags
= IORESOURCE_IRQ
,
297 static struct platform_device mv78xx0_ge00_shared
= {
298 .name
= MV643XX_ETH_SHARED_NAME
,
301 .platform_data
= &mv78xx0_ge00_shared_data
,
303 .num_resources
= ARRAY_SIZE(mv78xx0_ge00_shared_resources
),
304 .resource
= mv78xx0_ge00_shared_resources
,
307 static struct resource mv78xx0_ge00_resources
[] = {
310 .start
= IRQ_MV78XX0_GE00_SUM
,
311 .end
= IRQ_MV78XX0_GE00_SUM
,
312 .flags
= IORESOURCE_IRQ
,
316 static struct platform_device mv78xx0_ge00
= {
317 .name
= MV643XX_ETH_NAME
,
320 .resource
= mv78xx0_ge00_resources
,
323 void __init
mv78xx0_ge00_init(struct mv643xx_eth_platform_data
*eth_data
)
325 eth_data
->shared
= &mv78xx0_ge00_shared
;
326 mv78xx0_ge00
.dev
.platform_data
= eth_data
;
328 platform_device_register(&mv78xx0_ge00_shared
);
329 platform_device_register(&mv78xx0_ge00
);
333 /*****************************************************************************
335 ****************************************************************************/
336 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data
= {
338 .dram
= &mv78xx0_mbus_dram_info
,
339 .shared_smi
= &mv78xx0_ge00_shared
,
342 static struct resource mv78xx0_ge01_shared_resources
[] = {
345 .start
= GE01_PHYS_BASE
+ 0x2000,
346 .end
= GE01_PHYS_BASE
+ 0x3fff,
347 .flags
= IORESOURCE_MEM
,
351 static struct platform_device mv78xx0_ge01_shared
= {
352 .name
= MV643XX_ETH_SHARED_NAME
,
355 .platform_data
= &mv78xx0_ge01_shared_data
,
358 .resource
= mv78xx0_ge01_shared_resources
,
361 static struct resource mv78xx0_ge01_resources
[] = {
364 .start
= IRQ_MV78XX0_GE01_SUM
,
365 .end
= IRQ_MV78XX0_GE01_SUM
,
366 .flags
= IORESOURCE_IRQ
,
370 static struct platform_device mv78xx0_ge01
= {
371 .name
= MV643XX_ETH_NAME
,
374 .resource
= mv78xx0_ge01_resources
,
377 void __init
mv78xx0_ge01_init(struct mv643xx_eth_platform_data
*eth_data
)
379 eth_data
->shared
= &mv78xx0_ge01_shared
;
380 mv78xx0_ge01
.dev
.platform_data
= eth_data
;
382 platform_device_register(&mv78xx0_ge01_shared
);
383 platform_device_register(&mv78xx0_ge01
);
387 /*****************************************************************************
389 ****************************************************************************/
390 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data
= {
392 .dram
= &mv78xx0_mbus_dram_info
,
393 .shared_smi
= &mv78xx0_ge00_shared
,
396 static struct resource mv78xx0_ge10_shared_resources
[] = {
399 .start
= GE10_PHYS_BASE
+ 0x2000,
400 .end
= GE10_PHYS_BASE
+ 0x3fff,
401 .flags
= IORESOURCE_MEM
,
405 static struct platform_device mv78xx0_ge10_shared
= {
406 .name
= MV643XX_ETH_SHARED_NAME
,
409 .platform_data
= &mv78xx0_ge10_shared_data
,
412 .resource
= mv78xx0_ge10_shared_resources
,
415 static struct resource mv78xx0_ge10_resources
[] = {
418 .start
= IRQ_MV78XX0_GE10_SUM
,
419 .end
= IRQ_MV78XX0_GE10_SUM
,
420 .flags
= IORESOURCE_IRQ
,
424 static struct platform_device mv78xx0_ge10
= {
425 .name
= MV643XX_ETH_NAME
,
428 .resource
= mv78xx0_ge10_resources
,
431 void __init
mv78xx0_ge10_init(struct mv643xx_eth_platform_data
*eth_data
)
433 eth_data
->shared
= &mv78xx0_ge10_shared
;
434 mv78xx0_ge10
.dev
.platform_data
= eth_data
;
436 platform_device_register(&mv78xx0_ge10_shared
);
437 platform_device_register(&mv78xx0_ge10
);
441 /*****************************************************************************
443 ****************************************************************************/
444 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data
= {
446 .dram
= &mv78xx0_mbus_dram_info
,
447 .shared_smi
= &mv78xx0_ge00_shared
,
450 static struct resource mv78xx0_ge11_shared_resources
[] = {
453 .start
= GE11_PHYS_BASE
+ 0x2000,
454 .end
= GE11_PHYS_BASE
+ 0x3fff,
455 .flags
= IORESOURCE_MEM
,
459 static struct platform_device mv78xx0_ge11_shared
= {
460 .name
= MV643XX_ETH_SHARED_NAME
,
463 .platform_data
= &mv78xx0_ge11_shared_data
,
466 .resource
= mv78xx0_ge11_shared_resources
,
469 static struct resource mv78xx0_ge11_resources
[] = {
472 .start
= IRQ_MV78XX0_GE11_SUM
,
473 .end
= IRQ_MV78XX0_GE11_SUM
,
474 .flags
= IORESOURCE_IRQ
,
478 static struct platform_device mv78xx0_ge11
= {
479 .name
= MV643XX_ETH_NAME
,
482 .resource
= mv78xx0_ge11_resources
,
485 void __init
mv78xx0_ge11_init(struct mv643xx_eth_platform_data
*eth_data
)
487 eth_data
->shared
= &mv78xx0_ge11_shared
;
488 mv78xx0_ge11
.dev
.platform_data
= eth_data
;
490 platform_device_register(&mv78xx0_ge11_shared
);
491 platform_device_register(&mv78xx0_ge11
);
495 /*****************************************************************************
497 ****************************************************************************/
498 static struct resource mv78xx0_sata_resources
[] = {
501 .start
= SATA_PHYS_BASE
,
502 .end
= SATA_PHYS_BASE
+ 0x5000 - 1,
503 .flags
= IORESOURCE_MEM
,
506 .start
= IRQ_MV78XX0_SATA
,
507 .end
= IRQ_MV78XX0_SATA
,
508 .flags
= IORESOURCE_IRQ
,
512 static struct platform_device mv78xx0_sata
= {
516 .coherent_dma_mask
= 0xffffffff,
518 .num_resources
= ARRAY_SIZE(mv78xx0_sata_resources
),
519 .resource
= mv78xx0_sata_resources
,
522 void __init
mv78xx0_sata_init(struct mv_sata_platform_data
*sata_data
)
524 sata_data
->dram
= &mv78xx0_mbus_dram_info
;
525 mv78xx0_sata
.dev
.platform_data
= sata_data
;
526 platform_device_register(&mv78xx0_sata
);
530 /*****************************************************************************
532 ****************************************************************************/
533 static struct plat_serial8250_port mv78xx0_uart0_data
[] = {
535 .mapbase
= UART0_PHYS_BASE
,
536 .membase
= (char *)UART0_VIRT_BASE
,
537 .irq
= IRQ_MV78XX0_UART_0
,
538 .flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
,
546 static struct resource mv78xx0_uart0_resources
[] = {
548 .start
= UART0_PHYS_BASE
,
549 .end
= UART0_PHYS_BASE
+ 0xff,
550 .flags
= IORESOURCE_MEM
,
552 .start
= IRQ_MV78XX0_UART_0
,
553 .end
= IRQ_MV78XX0_UART_0
,
554 .flags
= IORESOURCE_IRQ
,
558 static struct platform_device mv78xx0_uart0
= {
559 .name
= "serial8250",
562 .platform_data
= mv78xx0_uart0_data
,
564 .resource
= mv78xx0_uart0_resources
,
565 .num_resources
= ARRAY_SIZE(mv78xx0_uart0_resources
),
568 void __init
mv78xx0_uart0_init(void)
570 platform_device_register(&mv78xx0_uart0
);
574 /*****************************************************************************
576 ****************************************************************************/
577 static struct plat_serial8250_port mv78xx0_uart1_data
[] = {
579 .mapbase
= UART1_PHYS_BASE
,
580 .membase
= (char *)UART1_VIRT_BASE
,
581 .irq
= IRQ_MV78XX0_UART_1
,
582 .flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
,
590 static struct resource mv78xx0_uart1_resources
[] = {
592 .start
= UART1_PHYS_BASE
,
593 .end
= UART1_PHYS_BASE
+ 0xff,
594 .flags
= IORESOURCE_MEM
,
596 .start
= IRQ_MV78XX0_UART_1
,
597 .end
= IRQ_MV78XX0_UART_1
,
598 .flags
= IORESOURCE_IRQ
,
602 static struct platform_device mv78xx0_uart1
= {
603 .name
= "serial8250",
606 .platform_data
= mv78xx0_uart1_data
,
608 .resource
= mv78xx0_uart1_resources
,
609 .num_resources
= ARRAY_SIZE(mv78xx0_uart1_resources
),
612 void __init
mv78xx0_uart1_init(void)
614 platform_device_register(&mv78xx0_uart1
);
618 /*****************************************************************************
620 ****************************************************************************/
621 static struct plat_serial8250_port mv78xx0_uart2_data
[] = {
623 .mapbase
= UART2_PHYS_BASE
,
624 .membase
= (char *)UART2_VIRT_BASE
,
625 .irq
= IRQ_MV78XX0_UART_2
,
626 .flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
,
634 static struct resource mv78xx0_uart2_resources
[] = {
636 .start
= UART2_PHYS_BASE
,
637 .end
= UART2_PHYS_BASE
+ 0xff,
638 .flags
= IORESOURCE_MEM
,
640 .start
= IRQ_MV78XX0_UART_2
,
641 .end
= IRQ_MV78XX0_UART_2
,
642 .flags
= IORESOURCE_IRQ
,
646 static struct platform_device mv78xx0_uart2
= {
647 .name
= "serial8250",
650 .platform_data
= mv78xx0_uart2_data
,
652 .resource
= mv78xx0_uart2_resources
,
653 .num_resources
= ARRAY_SIZE(mv78xx0_uart2_resources
),
656 void __init
mv78xx0_uart2_init(void)
658 platform_device_register(&mv78xx0_uart2
);
662 /*****************************************************************************
664 ****************************************************************************/
665 static struct plat_serial8250_port mv78xx0_uart3_data
[] = {
667 .mapbase
= UART3_PHYS_BASE
,
668 .membase
= (char *)UART3_VIRT_BASE
,
669 .irq
= IRQ_MV78XX0_UART_3
,
670 .flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
,
678 static struct resource mv78xx0_uart3_resources
[] = {
680 .start
= UART3_PHYS_BASE
,
681 .end
= UART3_PHYS_BASE
+ 0xff,
682 .flags
= IORESOURCE_MEM
,
684 .start
= IRQ_MV78XX0_UART_3
,
685 .end
= IRQ_MV78XX0_UART_3
,
686 .flags
= IORESOURCE_IRQ
,
690 static struct platform_device mv78xx0_uart3
= {
691 .name
= "serial8250",
694 .platform_data
= mv78xx0_uart3_data
,
696 .resource
= mv78xx0_uart3_resources
,
697 .num_resources
= ARRAY_SIZE(mv78xx0_uart3_resources
),
700 void __init
mv78xx0_uart3_init(void)
702 platform_device_register(&mv78xx0_uart3
);
706 /*****************************************************************************
708 ****************************************************************************/
709 static void mv78xx0_timer_init(void)
711 orion_time_init(IRQ_MV78XX0_TIMER_1
, get_tclk());
714 struct sys_timer mv78xx0_timer
= {
715 .init
= mv78xx0_timer_init
,
719 /*****************************************************************************
721 ****************************************************************************/
722 static int __init
is_l2_writethrough(void)
724 return !!(readl(CPU_CONTROL
) & L2_WRITETHROUGH
);
727 void __init
mv78xx0_init(void)
735 core_index
= mv78xx0_core_index();
737 get_pclk_l2clk(hclk
, core_index
, &pclk
, &l2clk
);
740 printk(KERN_INFO
"MV78xx0 core #%d, ", core_index
);
741 printk("PCLK = %dMHz, ", (pclk
+ 499999) / 1000000);
742 printk("L2 = %dMHz, ", (l2clk
+ 499999) / 1000000);
743 printk("HCLK = %dMHz, ", (hclk
+ 499999) / 1000000);
744 printk("TCLK = %dMHz\n", (tclk
+ 499999) / 1000000);
746 mv78xx0_setup_cpu_mbus();
748 #ifdef CONFIG_CACHE_FEROCEON_L2
749 feroceon_l2_init(is_l2_writethrough());
752 mv78xx0_ge00_shared_data
.t_clk
= tclk
;
753 mv78xx0_ge01_shared_data
.t_clk
= tclk
;
754 mv78xx0_ge10_shared_data
.t_clk
= tclk
;
755 mv78xx0_ge11_shared_data
.t_clk
= tclk
;
756 mv78xx0_uart0_data
[0].uartclk
= tclk
;
757 mv78xx0_uart1_data
[0].uartclk
= tclk
;
758 mv78xx0_uart2_data
[0].uartclk
= tclk
;
759 mv78xx0_uart3_data
[0].uartclk
= tclk
;