2 * Symmetric Multi Processing (SMP) support for Armada XP
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Yehuda Yitschak <yehuday@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
16 * This file implements the routines for preparing the SMP infrastructure
17 * and waking up the secondary CPUs
20 #include <linux/init.h>
21 #include <linux/smp.h>
22 #include <linux/clk.h>
24 #include <linux/mbus.h>
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
28 #include "armada-370-xp.h"
30 #include "coherency.h"
32 void __init
set_secondary_cpus_clock(void)
36 struct clk
*cpu_clk
= NULL
;
37 struct device_node
*np
= NULL
;
39 thiscpu
= smp_processor_id();
40 for_each_node_by_type(np
, "cpu") {
44 err
= of_property_read_u32(np
, "reg", &cpu
);
49 cpu_clk
= of_clk_get(np
, 0);
53 if (WARN_ON(IS_ERR(cpu_clk
)))
55 clk_prepare_enable(cpu_clk
);
56 rate
= clk_get_rate(cpu_clk
);
58 /* set all the other CPU clk to the same rate than the boot CPU */
59 for_each_node_by_type(np
, "cpu") {
63 err
= of_property_read_u32(np
, "reg", &cpu
);
68 cpu_clk
= of_clk_get(np
, 0);
69 clk_set_rate(cpu_clk
, rate
);
74 static void armada_xp_secondary_init(unsigned int cpu
)
76 armada_xp_mpic_smp_cpu_init();
79 static int armada_xp_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
81 pr_info("Booting CPU %d\n", cpu
);
83 armada_xp_boot_cpu(cpu
, armada_xp_secondary_startup
);
88 static void __init
armada_xp_smp_init_cpus(void)
90 struct device_node
*np
;
91 unsigned int i
, ncores
;
93 np
= of_find_node_by_name(NULL
, "cpus");
95 panic("No 'cpus' node found\n");
97 ncores
= of_get_child_count(np
);
98 if (ncores
== 0 || ncores
> ARMADA_XP_MAX_CPUS
)
99 panic("Invalid number of CPUs in DT\n");
101 /* Limit possible CPUs to defconfig */
102 if (ncores
> nr_cpu_ids
) {
103 pr_warn("SMP: %d CPUs physically present. Only %d configured.",
105 pr_warn("Clipping CPU count to %d\n", nr_cpu_ids
);
109 for (i
= 0; i
< ncores
; i
++)
110 set_cpu_possible(i
, true);
112 set_smp_cross_call(armada_mpic_send_doorbell
);
115 void __init
armada_xp_smp_prepare_cpus(unsigned int max_cpus
)
117 set_secondary_cpus_clock();
119 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
120 mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M
);
123 struct smp_operations armada_xp_smp_ops __initdata
= {
124 .smp_init_cpus
= armada_xp_smp_init_cpus
,
125 .smp_prepare_cpus
= armada_xp_smp_prepare_cpus
,
126 .smp_secondary_init
= armada_xp_secondary_init
,
127 .smp_boot_secondary
= armada_xp_boot_secondary
,
128 #ifdef CONFIG_HOTPLUG_CPU
129 .cpu_die
= armada_xp_cpu_die
,