arch/arm/mach-mvebu/pmsu_ll.S

   1 /*
   2  * Copyright (C) 2014 Marvell
   3  *
   4  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   5  * Gregory Clement <gregory.clement@free-electrons.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2.  This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/linkage.h>
  13 #include <asm/assembler.h>
  14
  15 /*
  16  * This is the entry point through which CPUs exiting cpuidle deep
  17  * idle state are going.
  18  */
  19 ENTRY(armada_370_xp_cpu_resume)
  20 ARM_BE8(setend  be )                    @ go BE8 if entered LE
  21         bl      ll_add_cpu_to_smp_group
  22         bl      ll_enable_coherency
  23         b       cpu_resume
  24 ENDPROC(armada_370_xp_cpu_resume)
  25
  26 ENTRY(armada_38x_cpu_resume)
  27         /* do we need it for Armada 38x*/
  28 ARM_BE8(setend  be )                    @ go BE8 if entered LE
  29         bl      v7_invalidate_l1
  30         mrc     p15, 4, r1, c15, c0     @ get SCU base address
  31         orr     r1, r1, #0x8            @ SCU CPU Power Status Register
  32         mrc     15, 0, r0, cr0, cr0, 5  @ get the CPU ID
  33         and     r0, r0, #15
  34         add     r1, r1, r0
  35         mov     r0, #0x0
  36         strb    r0, [r1]                @ switch SCU power state to Normal mode
  37         b       cpu_resume
  38 ENDPROC(armada_38x_cpu_resume)
  39
  40 .global mvebu_boot_wa_start
  41 .global mvebu_boot_wa_end
  42
  43 /* The following code will be executed from SRAM */
  44 ENTRY(mvebu_boot_wa_start)
  45 mvebu_boot_wa_start:
  46 ARM_BE8(setend  be)
  47         adr     r0, 1f
  48         ldr     r0, [r0]                @ load the address of the
  49                                         @ resume register
  50         ldr     r0, [r0]                @ load the value in the
  51                                         @ resume register
  52 ARM_BE8(rev     r0, r0)                 @ the value is stored LE
  53         mov     pc, r0                  @ jump to this value
  54 /*
  55  * the last word of this piece of code will be filled by the physical
  56  * address of the boot address register just after being copied in SRAM
  57  */
  58 1:
  59         .long   .
  60 mvebu_boot_wa_end:
  61 ENDPROC(mvebu_boot_wa_end)