arch/arm/mach-mvebu/system-controller.c

   1 /*
   2  * System controller support for Armada 370, 375 and XP platforms.
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * The Armada 370, 375 and Armada XP SoCs have a range of
  15  * miscellaneous registers, that do not belong to a particular device,
  16  * but rather provide system-level features. This basic
  17  * system-controller driver provides a device tree binding for those
  18  * registers, and implements utility functions offering various
  19  * features related to those registers.
  20  *
  21  * For now, the feature set is limited to restarting the platform by a
  22  * soft-reset, but it might be extended in the future.
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/of_address.h>
  28 #include <linux/io.h>
  29 #include <linux/reboot.h>
  30 #include "common.h"
  31
  32 static void __iomem *system_controller_base;
  33
  34 struct mvebu_system_controller {
  35         u32 rstoutn_mask_offset;
  36         u32 system_soft_reset_offset;
  37
  38         u32 rstoutn_mask_reset_out_en;
  39         u32 system_soft_reset;
  40
  41         u32 resume_boot_addr;
  42 };
  43 static struct mvebu_system_controller *mvebu_sc;
  44
  45 static const struct mvebu_system_controller armada_370_xp_system_controller = {
  46         .rstoutn_mask_offset = 0x60,
  47         .system_soft_reset_offset = 0x64,
  48         .rstoutn_mask_reset_out_en = 0x1,
  49         .system_soft_reset = 0x1,
  50 };
  51
  52 static const struct mvebu_system_controller armada_375_system_controller = {
  53         .rstoutn_mask_offset = 0x54,
  54         .system_soft_reset_offset = 0x58,
  55         .rstoutn_mask_reset_out_en = 0x1,
  56         .system_soft_reset = 0x1,
  57         .resume_boot_addr = 0xd4,
  58 };
  59
  60 static const struct mvebu_system_controller orion_system_controller = {
  61         .rstoutn_mask_offset = 0x108,
  62         .system_soft_reset_offset = 0x10c,
  63         .rstoutn_mask_reset_out_en = 0x4,
  64         .system_soft_reset = 0x1,
  65 };
  66
  67 static const struct of_device_id of_system_controller_table[] = {
  68         {
  69                 .compatible = "marvell,orion-system-controller",
  70                 .data = (void *) &orion_system_controller,
  71         }, {
  72                 .compatible = "marvell,armada-370-xp-system-controller",
  73                 .data = (void *) &armada_370_xp_system_controller,
  74         }, {
  75                 .compatible = "marvell,armada-375-system-controller",
  76                 .data = (void *) &armada_375_system_controller,
  77         },
  78         { /* end of list */ },
  79 };
  80
  81 void mvebu_restart(enum reboot_mode mode, const char *cmd)
  82 {
  83         if (!system_controller_base) {
  84                 pr_err("Cannot restart, system-controller not available: check the device tree\n");
  85         } else {
  86                 /*
  87                  * Enable soft reset to assert RSTOUTn.
  88                  */
  89                 writel(mvebu_sc->rstoutn_mask_reset_out_en,
  90                         system_controller_base +
  91                         mvebu_sc->rstoutn_mask_offset);
  92                 /*
  93                  * Assert soft reset.
  94                  */
  95                 writel(mvebu_sc->system_soft_reset,
  96                         system_controller_base +
  97                         mvebu_sc->system_soft_reset_offset);
  98         }
  99
 100         while (1)
 101                 ;
 102 }
 103
 104 #ifdef CONFIG_SMP
 105 void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
 106 {
 107         BUG_ON(system_controller_base == NULL);
 108         BUG_ON(mvebu_sc->resume_boot_addr == 0);
 109         writel(virt_to_phys(boot_addr), system_controller_base +
 110                mvebu_sc->resume_boot_addr);
 111 }
 112 #endif
 113
 114 static int __init mvebu_system_controller_init(void)
 115 {
 116         const struct of_device_id *match;
 117         struct device_node *np;
 118
 119         np = of_find_matching_node_and_match(NULL, of_system_controller_table,
 120                                              &match);
 121         if (np) {
 122                 system_controller_base = of_iomap(np, 0);
 123                 mvebu_sc = (struct mvebu_system_controller *)match->data;
 124                 of_node_put(np);
 125         }
 126
 127         return 0;
 128 }
 129
 130 early_initcall(mvebu_system_controller_init);