arch/arm/mach-mx2/devices.c

   1 /*
   2  * Author: MontaVista Software, Inc.
   3  *       <source@mvista.com>
   4  *
   5  * Based on the OMAP devices.c
   6  *
   7  * 2005 (c) MontaVista Software, Inc. This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  *
  12  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27  * MA 02110-1301, USA.
  28  */
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/gpio.h>
  34
  35 #include <mach/irqs.h>
  36 #include <mach/hardware.h>
  37 #include <mach/common.h>
  38 #include <mach/mmc.h>
  39
  40 #include "devices.h"
  41
  42 /*
  43  * General Purpose Timer
  44  * - i.MX21: 3 timers
  45  * - i.MX27: 6 timers
  46  */
  47
  48 /* We use gpt0 as system timer, so do not add a device for this one */
  49
  50 static struct resource timer1_resources[] = {
  51         {
  52                 .start  = GPT2_BASE_ADDR,
  53                 .end    = GPT2_BASE_ADDR + 0x17,
  54                 .flags  = IORESOURCE_MEM,
  55         }, {
  56                 .start   = MXC_INT_GPT2,
  57                 .end     = MXC_INT_GPT2,
  58                 .flags   = IORESOURCE_IRQ,
  59         }
  60 };
  61
  62 struct platform_device mxc_gpt1 = {
  63         .name = "imx_gpt",
  64         .id = 1,
  65         .num_resources = ARRAY_SIZE(timer1_resources),
  66         .resource = timer1_resources,
  67 };
  68
  69 static struct resource timer2_resources[] = {
  70         {
  71                 .start  = GPT3_BASE_ADDR,
  72                 .end    = GPT3_BASE_ADDR + 0x17,
  73                 .flags  = IORESOURCE_MEM,
  74         }, {
  75                 .start   = MXC_INT_GPT3,
  76                 .end     = MXC_INT_GPT3,
  77                 .flags   = IORESOURCE_IRQ,
  78         }
  79 };
  80
  81 struct platform_device mxc_gpt2 = {
  82         .name = "imx_gpt",
  83         .id = 2,
  84         .num_resources = ARRAY_SIZE(timer2_resources),
  85         .resource = timer2_resources,
  86 };
  87
  88 #ifdef CONFIG_MACH_MX27
  89 static struct resource timer3_resources[] = {
  90         {
  91                 .start  = GPT4_BASE_ADDR,
  92                 .end    = GPT4_BASE_ADDR + 0x17,
  93                 .flags  = IORESOURCE_MEM,
  94         }, {
  95                 .start   = MXC_INT_GPT4,
  96                 .end     = MXC_INT_GPT4,
  97                 .flags   = IORESOURCE_IRQ,
  98         }
  99 };
 100
 101 struct platform_device mxc_gpt3 = {
 102         .name = "imx_gpt",
 103         .id = 3,
 104         .num_resources = ARRAY_SIZE(timer3_resources),
 105         .resource = timer3_resources,
 106 };
 107
 108 static struct resource timer4_resources[] = {
 109         {
 110                 .start  = GPT5_BASE_ADDR,
 111                 .end    = GPT5_BASE_ADDR + 0x17,
 112                 .flags  = IORESOURCE_MEM,
 113         }, {
 114                 .start   = MXC_INT_GPT5,
 115                 .end     = MXC_INT_GPT5,
 116                 .flags   = IORESOURCE_IRQ,
 117         }
 118 };
 119
 120 struct platform_device mxc_gpt4 = {
 121         .name = "imx_gpt",
 122         .id = 4,
 123         .num_resources = ARRAY_SIZE(timer4_resources),
 124         .resource = timer4_resources,
 125 };
 126
 127 static struct resource timer5_resources[] = {
 128         {
 129                 .start  = GPT6_BASE_ADDR,
 130                 .end    = GPT6_BASE_ADDR + 0x17,
 131                 .flags  = IORESOURCE_MEM,
 132         }, {
 133                 .start   = MXC_INT_GPT6,
 134                 .end     = MXC_INT_GPT6,
 135                 .flags   = IORESOURCE_IRQ,
 136         }
 137 };
 138
 139 struct platform_device mxc_gpt5 = {
 140         .name = "imx_gpt",
 141         .id = 5,
 142         .num_resources = ARRAY_SIZE(timer5_resources),
 143         .resource = timer5_resources,
 144 };
 145 #endif
 146
 147 /*
 148  * Watchdog:
 149  * - i.MX1
 150  * - i.MX21
 151  * - i.MX27
 152  */
 153 static struct resource mxc_wdt_resources[] = {
 154         {
 155                 .start  = WDOG_BASE_ADDR,
 156                 .end    = WDOG_BASE_ADDR + 0x30,
 157                 .flags  = IORESOURCE_MEM,
 158         },
 159 };
 160
 161 struct platform_device mxc_wdt = {
 162         .name = "mxc_wdt",
 163         .id = 0,
 164         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
 165         .resource = mxc_wdt_resources,
 166 };
 167
 168 static struct resource mxc_w1_master_resources[] = {
 169         {
 170                 .start = OWIRE_BASE_ADDR,
 171                 .end   = OWIRE_BASE_ADDR + SZ_4K - 1,
 172                 .flags = IORESOURCE_MEM,
 173         },
 174 };
 175
 176 struct platform_device mxc_w1_master_device = {
 177         .name = "mxc_w1",
 178         .id = 0,
 179         .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
 180         .resource = mxc_w1_master_resources,
 181 };
 182
 183 static struct resource mxc_nand_resources[] = {
 184         {
 185                 .start  = NFC_BASE_ADDR,
 186                 .end    = NFC_BASE_ADDR + 0xfff,
 187                 .flags  = IORESOURCE_MEM,
 188         }, {
 189                 .start  = MXC_INT_NANDFC,
 190                 .end    = MXC_INT_NANDFC,
 191                 .flags  = IORESOURCE_IRQ,
 192         },
 193 };
 194
 195 struct platform_device mxc_nand_device = {
 196         .name = "mxc_nand",
 197         .id = 0,
 198         .num_resources = ARRAY_SIZE(mxc_nand_resources),
 199         .resource = mxc_nand_resources,
 200 };
 201
 202 /*
 203  * lcdc:
 204  * - i.MX1: the basic controller
 205  * - i.MX21: to be checked
 206  * - i.MX27: like i.MX1, with slightly variations
 207  */
 208 static struct resource mxc_fb[] = {
 209         {
 210                 .start = LCDC_BASE_ADDR,
 211                 .end   = LCDC_BASE_ADDR + 0xFFF,
 212                 .flags = IORESOURCE_MEM,
 213         }, {
 214                 .start = MXC_INT_LCDC,
 215                 .end   = MXC_INT_LCDC,
 216                 .flags = IORESOURCE_IRQ,
 217         }
 218 };
 219
 220 /* mxc lcd driver */
 221 struct platform_device mxc_fb_device = {
 222         .name = "imx-fb",
 223         .id = 0,
 224         .num_resources = ARRAY_SIZE(mxc_fb),
 225         .resource = mxc_fb,
 226         .dev = {
 227                 .coherent_dma_mask = 0xFFFFFFFF,
 228         },
 229 };
 230
 231 #ifdef CONFIG_MACH_MX27
 232 static struct resource mxc_fec_resources[] = {
 233         {
 234                 .start  = FEC_BASE_ADDR,
 235                 .end    = FEC_BASE_ADDR + 0xfff,
 236                 .flags  = IORESOURCE_MEM,
 237         }, {
 238                 .start  = MXC_INT_FEC,
 239                 .end    = MXC_INT_FEC,
 240                 .flags  = IORESOURCE_IRQ,
 241         },
 242 };
 243
 244 struct platform_device mxc_fec_device = {
 245         .name = "fec",
 246         .id = 0,
 247         .num_resources = ARRAY_SIZE(mxc_fec_resources),
 248         .resource = mxc_fec_resources,
 249 };
 250 #endif
 251
 252 static struct resource mxc_i2c_1_resources[] = {
 253         {
 254                 .start  = I2C_BASE_ADDR,
 255                 .end    = I2C_BASE_ADDR + 0x0fff,
 256                 .flags  = IORESOURCE_MEM,
 257         }, {
 258                 .start  = MXC_INT_I2C,
 259                 .end    = MXC_INT_I2C,
 260                 .flags  = IORESOURCE_IRQ,
 261         }
 262 };
 263
 264 struct platform_device mxc_i2c_device0 = {
 265         .name = "imx-i2c",
 266         .id = 0,
 267         .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
 268         .resource = mxc_i2c_1_resources,
 269 };
 270
 271 #ifdef CONFIG_MACH_MX27
 272 static struct resource mxc_i2c_2_resources[] = {
 273         {
 274                 .start  = I2C2_BASE_ADDR,
 275                 .end    = I2C2_BASE_ADDR + 0x0fff,
 276                 .flags  = IORESOURCE_MEM,
 277         }, {
 278                 .start  = MXC_INT_I2C2,
 279                 .end    = MXC_INT_I2C2,
 280                 .flags  = IORESOURCE_IRQ,
 281         }
 282 };
 283
 284 struct platform_device mxc_i2c_device1 = {
 285         .name = "imx-i2c",
 286         .id = 1,
 287         .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
 288         .resource = mxc_i2c_2_resources,
 289 };
 290 #endif
 291
 292 static struct resource mxc_pwm_resources[] = {
 293         {
 294                 .start  = PWM_BASE_ADDR,
 295                 .end    = PWM_BASE_ADDR + 0x0fff,
 296                 .flags  = IORESOURCE_MEM,
 297         }, {
 298                 .start   = MXC_INT_PWM,
 299                 .end     = MXC_INT_PWM,
 300                 .flags   = IORESOURCE_IRQ,
 301         }
 302 };
 303
 304 struct platform_device mxc_pwm_device = {
 305         .name = "mxc_pwm",
 306         .id = 0,
 307         .num_resources = ARRAY_SIZE(mxc_pwm_resources),
 308         .resource = mxc_pwm_resources,
 309 };
 310
 311 /*
 312  * Resource definition for the MXC SDHC
 313  */
 314 static struct resource mxc_sdhc1_resources[] = {
 315         {
 316                 .start = SDHC1_BASE_ADDR,
 317                 .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
 318                 .flags = IORESOURCE_MEM,
 319         }, {
 320                 .start = MXC_INT_SDHC1,
 321                 .end   = MXC_INT_SDHC1,
 322                 .flags = IORESOURCE_IRQ,
 323         }, {
 324                 .start  = DMA_REQ_SDHC1,
 325                 .end    = DMA_REQ_SDHC1,
 326                 .flags  = IORESOURCE_DMA,
 327         },
 328 };
 329
 330 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
 331
 332 struct platform_device mxc_sdhc_device0 = {
 333        .name           = "mxc-mmc",
 334        .id             = 0,
 335        .dev            = {
 336                .dma_mask = &mxc_sdhc1_dmamask,
 337                .coherent_dma_mask = 0xffffffff,
 338        },
 339        .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
 340        .resource       = mxc_sdhc1_resources,
 341 };
 342
 343 static struct resource mxc_sdhc2_resources[] = {
 344         {
 345                 .start = SDHC2_BASE_ADDR,
 346                 .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
 347                 .flags = IORESOURCE_MEM,
 348         }, {
 349                 .start = MXC_INT_SDHC2,
 350                 .end   = MXC_INT_SDHC2,
 351                 .flags = IORESOURCE_IRQ,
 352         }, {
 353                 .start  = DMA_REQ_SDHC2,
 354                 .end    = DMA_REQ_SDHC2,
 355                 .flags  = IORESOURCE_DMA,
 356         },
 357 };
 358
 359 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
 360
 361 struct platform_device mxc_sdhc_device1 = {
 362        .name           = "mxc-mmc",
 363        .id             = 1,
 364        .dev            = {
 365                .dma_mask = &mxc_sdhc2_dmamask,
 366                .coherent_dma_mask = 0xffffffff,
 367        },
 368        .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
 369        .resource       = mxc_sdhc2_resources,
 370 };
 371
 372 static struct resource otg_resources[] = {
 373         {
 374                 .start  = OTG_BASE_ADDR,
 375                 .end    = OTG_BASE_ADDR + 0x1ff,
 376                 .flags  = IORESOURCE_MEM,
 377         }, {
 378                 .start  = MXC_INT_USB3,
 379                 .end    = MXC_INT_USB3,
 380                 .flags  = IORESOURCE_IRQ,
 381         },
 382 };
 383
 384 static u64 otg_dmamask = 0xffffffffUL;
 385
 386 /* OTG gadget device */
 387 struct platform_device mxc_otg_udc_device = {
 388         .name           = "fsl-usb2-udc",
 389         .id             = -1,
 390         .dev            = {
 391                 .dma_mask               = &otg_dmamask,
 392                 .coherent_dma_mask      = 0xffffffffUL,
 393         },
 394         .resource       = otg_resources,
 395         .num_resources  = ARRAY_SIZE(otg_resources),
 396 };
 397
 398 /* OTG host */
 399 struct platform_device mxc_otg_host = {
 400         .name = "mxc-ehci",
 401         .id = 0,
 402         .dev = {
 403                 .coherent_dma_mask = 0xffffffff,
 404                 .dma_mask = &otg_dmamask,
 405         },
 406         .resource = otg_resources,
 407         .num_resources = ARRAY_SIZE(otg_resources),
 408 };
 409
 410 /* USB host 1 */
 411
 412 static u64 usbh1_dmamask = 0xffffffffUL;
 413
 414 static struct resource mxc_usbh1_resources[] = {
 415         {
 416                 .start = OTG_BASE_ADDR + 0x200,
 417                 .end = OTG_BASE_ADDR + 0x3ff,
 418                 .flags = IORESOURCE_MEM,
 419         }, {
 420                 .start = MXC_INT_USB1,
 421                 .end = MXC_INT_USB1,
 422                 .flags = IORESOURCE_IRQ,
 423         },
 424 };
 425
 426 struct platform_device mxc_usbh1 = {
 427         .name = "mxc-ehci",
 428         .id = 1,
 429         .dev = {
 430                 .coherent_dma_mask = 0xffffffff,
 431                 .dma_mask = &usbh1_dmamask,
 432         },
 433         .resource = mxc_usbh1_resources,
 434         .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
 435 };
 436
 437 /* USB host 2 */
 438 static u64 usbh2_dmamask = 0xffffffffUL;
 439
 440 static struct resource mxc_usbh2_resources[] = {
 441         {
 442                 .start = OTG_BASE_ADDR + 0x400,
 443                 .end = OTG_BASE_ADDR + 0x5ff,
 444                 .flags = IORESOURCE_MEM,
 445         }, {
 446                 .start = MXC_INT_USB2,
 447                 .end = MXC_INT_USB2,
 448                 .flags = IORESOURCE_IRQ,
 449         },
 450 };
 451
 452 struct platform_device mxc_usbh2 = {
 453         .name = "mxc-ehci",
 454         .id = 2,
 455         .dev = {
 456                 .coherent_dma_mask = 0xffffffff,
 457                 .dma_mask = &usbh2_dmamask,
 458         },
 459         .resource = mxc_usbh2_resources,
 460         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 461 };
 462
 463
 464 /* GPIO port description */
 465 static struct mxc_gpio_port imx_gpio_ports[] = {
 466         {
 467                 .chip.label = "gpio-0",
 468                 .irq = MXC_INT_GPIO,
 469                 .base = IO_ADDRESS(GPIO_BASE_ADDR),
 470                 .virtual_irq_start = MXC_GPIO_IRQ_START,
 471         }, {
 472                 .chip.label = "gpio-1",
 473                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
 474                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
 475         }, {
 476                 .chip.label = "gpio-2",
 477                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
 478                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
 479         }, {
 480                 .chip.label = "gpio-3",
 481                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
 482                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
 483         }, {
 484                 .chip.label = "gpio-4",
 485                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
 486                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
 487         }, {
 488                 .chip.label = "gpio-5",
 489                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
 490                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
 491         }
 492 };
 493
 494 int __init mxc_register_gpios(void)
 495 {
 496         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 497 }